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johann23
johann23
Associate II
March 26, 2013
Question

External SRAM (FSMC) poor performance

  • March 26, 2013
  • 3 replies
  • 1171 views
Posted on March 26, 2013 at 12:02

Dear all,

I have de

veloped a board on which

a STM32F205 microcontroller is connecte

d to an a

synchronous

external SRAM (ISSI IS61WV102416BLL

) which has

read/write access times of 10ns.

This

RAM is used as a

pic

ture buffer.

I configured the F

SMC bus as follows:

  • Normal mode (mode 1)

  • ADDSET = 2

    HCLK cycles

  • DATAST = 2

    HCLK cycles

where HCLK is 120MHz.

I measured

the NE and NWE lines

for one write ac

cess and saw that

ADD

SET

last

s

1.62us and the memory transaction, 8.52us

. Considering the memory

read/write access time of 10

ns and the

FSMC configuration

, I expected something more lik

e 16ns for ADDSET an

d 32ns for the memory transaction which is more that 200x

faster that

wha

t I have today

.

Am I missing something or where should I focus on to improve this poor memory performance?

Thank you

in advance for your help.

Regards

#stm32f205-sram-fsmc-performance
This topic has been closed for replies.

3 replies

Tesla DeLorean
Tesla DeLorean
Guru
March 26, 2013
Posted on March 26, 2013 at 15:42

That does seem awfully slow.

Perhaps you need to revisit your assumptions, and confirm the speed the core is running via MCO pins, or timer output.

Check the performance observed with one of the EVAL series boards using external memory.
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johann23
johann23Author
Associate II
March 27, 2013
Posted on March 27, 2013 at 09:09

T

hank

you clive1 for your answer.

As you suggested

,

I d

id some tests with the SRAM

of

STM3220G-EVAL board in order to

be sure that m

y code

was

working as expected

and the

measured write access time was near 40ns, which

is correct.

I found what w

as wrong

:

In my IDE (Crossworks), for w

hatever reas

on, the

configuration hea

der ''stm32f2xx.h'' used within the project was

another

one that t

he one specified in the project structure w

hich

defined

the

HSE value to 25MHz instead of 16MHz. I

updated the project struc

ture and now

, the

write access time of the SRAM is near 4

0ns.

frankmeyer9
frankmeyer9
Associate III
March 27, 2013
Posted on March 27, 2013 at 10:23

I believe changing the

''stm32f2xx.h''

header is generally not a good idea.

Using Crossworks too, I usually add the define for the HSE_VALUE to the project settings, and not directly into the header. The same applies for USE_STDPERIPH_DRIVER.

This is IMHO the way intended by ST.

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