Dual core stm32f4

[yavar_zarei]

Posted on February 20, 2014 at 08:45

For many control applications that we have a fast control loop that can not be interrupted and also have communications on CAN,USB,RS485,Ethernet,...it is better to have a dual core stm32 that one core must be Cortex M4(for control) and other one should be Cortex M3/M0(for comm tasks),there should be an internal shared dual port RAM for two cpu communication.

I think this product is needed for stm32 family.

[frankmeyer9]

Posted on February 20, 2014 at 09:01

Depending on the requirements of your applications, you may alsoconsider a Cortex R, which is above the Cortex M, performance-wise.

TI has a range of Cortex R silicons to offer....it is better to have a dual core stm32 that one core must be Cortex M4(for control) and other one should be Cortex M3/M0(for comm tasks)... I guess you alluding to the LPC43xx controllers. Might be an option, but multiprocessing introduces a whole new class of issues (and 'opportunities' for bugs), so I would think twice before starting in this field.

[chen]

Posted on February 20, 2014 at 10:27

Yes, fm is right, the STM32 line is not designed for multicore.

Try the lines fm suggested or the SPC56 line from ST, this is actually Cortex A which is far more powerful. ''For many control applications that we have a fast control loop'' There are many options here : 1) disable IRQs while in control loop 2) make the control loop a NMI IRQ 3) consider a hardware (electronic) solution for the control loop. 3) consider a seperate DSP processor. 4) consider 2 processors Coretx M3/4 + a Cortex M0 ''Might be an option, but multiprocessing introduces a whole new class of issues (and 'opportunities' for bugs), so I would think twice before starting in this field.'' I agree! Just going multi-threaded has enough problems!

[chen]

Posted on February 20, 2014 at 10:43

Hi

I have just thought about it again. ''For many control applications that we have a fast control loop'' This is a classic Real Time System. The first thing a RTS must do is define the response time. How will the system satisfy the response time?