Dual CAN on G491 (bare metal)

[Nickelgrass]

Hello,

I implemented a FDCAN in bare metal on the STM32G491 that works on FDCAN1 (with one unrelated problem). Now I need the second one too. So when I try to send over FDCAN2 only garbage comes out on the CAN bus. Yet the CRC is correct so it is actually sending but not the correct content. I send out the contents of the FDRAM over a uart to check and on both sending over FDCAN1 and FDCAN2 the content is correct. It seems that the FDCAN2 does not read from the correct FDRAM location. Are there two FDRAMs?

I use the same function for both:

void can_write(FDCAN_Global_TypeDef* can, uint32_t id, uint32_t data0, uint32_t data1)
{
	uint8_t index = 0;
	while((can->TXFQS&bit21) == bit21);
	index = ((can->TXFQS>>16)&0b11);
	FDRAM->tx_fifo[index].header[0] = id<<18;
	FDRAM->tx_fifo[index].header[1] = 8<<16;
	FDRAM->tx_fifo[index].data.word[0] = data0;
	FDRAM->tx_fifo[index].data.word[1] = data1;
	can->TXBAR |= (1<<index);
}

The other unrelated problem on FDCAN1 is if I call the can_write function twice directly after each other only the first message is sent. I would expect the FDCAN to get the second message out once the first is done. Basically I an going to use it with interrupts but I was just wondering why the second message did not get sent. The index is increased to 1 on the second .

Thanks

Kind regards

[SofLit]

Hello,

When you want to go with baremetal implementation and have issue, need to look at the HAL driver implementation and inspire from it.

[Nickelgrass]

Hi, thanks for the reply. I have already looked at the HAL extensively. But I could not see this information. 

[SofLit]

Which information?

You need to focus on the direct access to the reciters and how they were assigned and configured at each step.

Use for example step by step debugging to see the sequence of call and values.

[Nickelgrass]

The offset for the second FDCAN in the shared FDRAM. In the AN5348 or in the RM0440 it describes the start and end address for each FDCAN instance in the FDRAM. But it does not give me information on where this offset (or start addess of FDCAN2) needs to be configured.