Documentation bug. RM0090 DocID018909 rev 13 page 712

[Andrei Chichak]

Posted on October 12, 2016 at 22:26

The diagram of the IWDG (figure 213) has LSI as a 40KHz clock. The description of IWDG and LSI have it as a 32KHz clock.

Which is it? 40? 32? Adjustable?Andrei from The Great White North

[Tesla DeLorean]

Posted on October 12, 2016 at 23:24

Which is it? 40? 32? Adjustable?

Wildly variable, and process dependent? The Datasheet for the 405 implied 17-47 KHz range. With a typical of 32 KHzThe F1 was supposed to be 40 KHz, the one I did much testing with was closer to 37 KHz and wandered all over the place, even at static temperatures. So not something that can be effectively trimmed or calibratedThere have been some inferences that the LSI used by the IWDG is not the same as the RTC one, but either way you probably can't turn off the LSI when the watchdog is using it.

[Walid FTITI_O]

Posted on October 13, 2016 at 13:04

Hi chichak.andrei, 

The typical value of LSI is 32 KHz and not 40 KHz, as shown in the Table.106 just below figure.213 in RM0090. The  40KHz in IWDG diagram is a typo.There is a note below the table :

1. These timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Please

refer to the LSI oscillator characteristics table in the device datasheet for maximum and minimum values.Indeed, in the relevant datasheet ''DocID024244'', ''Table 42. LSI oscillator charachteristics'' confirms that typical value is 32KHz and maximum is 47 KHz.I submit a fix request to correct the typo indicated.Thank you for the feedback.-Hannibal-

[Tesla DeLorean]

Posted on October 13, 2016 at 17:29

Can you confirm if there are one or two LSI sources within the design?

If a single LSI source can you diagram the gating of that source with respect to RCC_CSR.LSION and the use by the watchdog?