DMA1, 2 and DMAMUX - how to do it?

[Mr_M_from_G]

Hello,

I am porting a project from STM32F4 to STM32H7. This project uses DMA1 and DMA2 with timer 8 and DAC and it works fine on STM32F4 but I can't get DMA running on STM32H7.

Up to now I understood it this way that all I have to do is set the right DMAMUX channel to the desired request ID. So I have these lines:

for DMA2_Stream1 to be triggered by TIM8-UP:
  DMAMUX1_Channel9->CCR = 51; // no sync, no event, no other stuff...
 
for DMA1 Stream5  to be triggered by DAC1 ch1:
DMAMUX1_Channel5->CCR = 67; 

In the DMA_Stream->CR I have to delete the channel selection used with STM32F4. All the rest s the same that works fine with F4.

I thought, from the things I read, that's all, but it doesn't work.

Now I read about domains and that DMA1 and DMA2 could not access all SRAM areas, escpeccially ITCM-RAM and DTCM-RAM, and Atollics ld-files puts everything in DTCM-RAM starting from 0x20000000. So I changed DMA sources to flash (transfer is from flash to peripheral) but still it doesn't work.

I am a bit suspicious that for DMAMUX there is no enable bit and no clock enable in an RCC register, at least I couldn't find anything.

So I would appreciate some help and explanations, maybe some example (without HAL if somehow possible).

Thank you very much

Martin

Thanks a lot

[Tesla DeLorean]

My expectation is the DMAMUX is clocked off the DMA unit, basically a more complex routing fabric compared to the channel/stream model with limited connectivity provided by earlier STM32 parts. Gating/enabling of the source at the DMA unit/channel itself, where it has a singular source, driven from the mux output. IC design favours the least complex implementation/arrangement.

With the H7 one has to be very careful about caching, and the lack of any coherency support from techniques like bus snooping on x86 and other architectures. On the CM7 you get to configure the MPU, and you can manage the flushing/invalidation of caches at a 32-byte granularity, to clear out write buffer, and force the read from memory of buffers you've changed via DMA outside the view of the processor.

[Mr_M_from_G]

Hello Clive,

thanks for your answer.

I follow your understanding of the signal path from mux to DMA channel.

Also I read again and some more, but still couldn't find anything about a clock enable. DMAMUX block diagram on page 676 of RM0433 shows a dmamux_hclk coming from AHB bus. This is also listed in Table 122 but never appears again in this RM.

I don't understand what you write about MPU and cache. I think this is a Cortex M7 function and therefore not in RM0433. But anyway, I try to do a DMA from flash to peripheral, this memory is not altered by my program. Please can you explain your assumption closer.

Still any help or hint is welcome.

Thanks very much

Martin

[Mr_M_from_G · Accepted solution]

Hello Clive,

I solved the problem just in time to go into a happy weekend.

But the cause of the problem is really evil.

As I wrote I use DMA1 and DMA2, the need for that came from the stream-channel connectivity on STM32F4. I initialize DMA2, then DMA1. For STM32H7 I added to these inits setting up DMAMUX.

Now as a genreral approach when initializing a peripheral I use RCC resetbits. What happened now is that using RCC_AHB1RSTR_DMA1RST not only resets DMA1 but also DMAMUX and not only the channels related to DMA1 but also those related to DMA2. So my DMAMUX settings from setting up DMA2 were gone.

I think that would be worth a note in the reference manual !!

Apart from this DMAMUX is a progress, eleminating previous limitations and it is straightforward to use.

I hope this helps someone else.

Martin