Posted on September 04, 2014 at 06:38Hello,
Here is an update which brings the NSS signal high. I have included
__HAL_SPI_DISABLE(&SpiHandle); // stops SPI clock
and this worked. This has to be done AFTER
while (HAL_SPI_GetState(&SpiHandle) != HAL_SPI_STATE_READY)
or it will not work. Presumably, this is after all flags get cleared and callbacks happen - at least this is what I stepped through.
My code implemented MOT mode 3, which has a continual NSS strobe for all 4 bytes I send, and NSS appears to go high 5uS after the last MOSI bit. My clock period is 2.875 uS, which puts this about 2 clocks after the last transmitted bit.
I have no idea how this port would work with MOT mode 0 or 2, which requires NSS to go high for ONE clock between bytes. If the clock rate is ~45MHz as advertised, there is NO WAY this will work. In addition, you would need at least a 2x clock to sample the SPI clk such that a timer would be able to raise NSS.
The second thing is having to disable the port to raise NSS counters logic that NSS should be coupled with each transmission (in my case, 4 bytes) so that NSS SHOULD fall 1/2 clock before SPI clk starts, and should go high 1/2 clock after the last bit. THEN you can stop the DMA channel, move the data out of the way, and stop the SPI port. I have used other CortexM3 micros from other vendors, and this is the way they all work - and I have logic analyzer traces showing this.
This appears to me to be a bug in the silicon, and there SHOULD be an errata explaining this and a workaround should be posted somewhere. There should be a display of all MOT modes running at the fastest speed allowed in the datasheet.
Dave Bassett
