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Direct Access to the SRAM


Hello, as part of my master's, I am required to process information received from some electronic system, I need to read 36 bits (output of 3 12 bit ADC) at the same time and process them and perform calculations and for that I need execution speed. I chose STM32H743ZGT6 and I wanted to know if ports B,D,G,E in this microcontroller have direct access to SRAM memory for fast reading of the ports and the possibility to process them after 4 clock cycles? That is, they will be stored in SRAM after 4 clock cycles


And if not , if there is any another option to do that?

Chief II


for really fast port access - the H7 is not the best choice. (very complex architecture, ports "far away" from core/ram)

Ports are on AHB4 bus and so on its speed there...see ds .



>possibility to process them after 4 clock cycles

Well, maybe ... fastest i got : 25ns at 200M core , so 5 core clks.

You will use DMA for this - right ? So just try (I didnt.), how many clks to RAM.

Maybe using BDMA -> to local 64KB RAM, it could be very fast (1 AHB4 clk , 4ns ?) and it dont block core, working on other RAM ....try it! and tell... 🙂


Compare with a H563 , i got : 4ns at 250M core, so 1 core clk.


Here ports on AHB2 bus with direct access  from core :


So a "more simple" architecture much better for a "simple" port access from core.


If you feel a post has answered your question, please click "Accept as Solution".

Congrats, your description is vague and unclear to the point of nonsensical.

"4 clock cycles": there's only about 137 clocks in the H7.  Do I get to pick?

"possibility to process": details matter.

People here will go out of their way to help and try to winkle out enough information to do so properly but questions like this really deserve only a resounding "Maybe, it depends.".  Try again, with some actual explanation.