Configuring HSE using CubeIDE on STM32H750

[NSR]

Using an STM32H750 part, I've lived with the slack tolerance of the HSI until coming to the UART where a speed of 9000 bps is experienced from a configured 9600 bps. This is too far out to be of any use at all and therefore have decided to put on an external clock. Fitting an 8 MHz XTAL with the required 20 pF capacitors I'm unable to get this working from the reconfiguring the CubeIDE. I've verified that the HSE is working by enabling MCO1 and directing the HSE out of that with a /8 modifer to give a 1 MHz signal from PA8 and the system continuing to function via the HSI at the PLL Source MUX. As soon as a switch to the HSE and reconfigure all the DIVMx for the PLLs from /8 to /1 (as moving from HSI 64 MHz to HSE 8 MHz) the system stalls at configuring PLL2; nothing comes out of the MCO1 either.

I've included the CubeIDE configured RCC code derived for the HSE.

void SystemClock_Config(void)
{
 LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
 while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4)
 {
 }
 LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
 LL_RCC_HSE_Enable();
 
  /* Wait till HSE is ready */
 while(LL_RCC_HSE_IsReady() != 1)
 {
 
 }
 LL_RCC_HSI48_Enable();
 
  /* Wait till HSI48 is ready */
 while(LL_RCC_HSI48_IsReady() != 1)
 {
 
 }
 
 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
 LL_RCC_PLL1P_Enable();
 LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_8_16);
 LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
 LL_RCC_PLL1_SetM(1);
 LL_RCC_PLL1_SetN(120);
 LL_RCC_PLL1_SetP(2);
 LL_RCC_PLL1_SetQ(2);
 LL_RCC_PLL1_SetR(2);
 LL_RCC_PLL1_Enable();
 
  /* Wait till PLL is ready */
 while(LL_RCC_PLL1_IsReady() != 1)
 {
 }
 
 LL_RCC_PLL2R_Enable();
 LL_RCC_PLL2_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_8_16);
 LL_RCC_PLL2_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
 LL_RCC_PLL2_SetM(1);
 LL_RCC_PLL2_SetN(80);
 LL_RCC_PLL2_SetP(4);
 LL_RCC_PLL2_SetQ(4);
 LL_RCC_PLL2_SetR(4);
 LL_RCC_PLL2_Enable();
 
  /* Wait till PLL is ready */
 while(LL_RCC_PLL2_IsReady() != 1) /* <----------- Controller hangs on this line */
 {
 }
 
 LL_RCC_PLL3P_Enable();
 LL_RCC_PLL3Q_Enable();
 LL_RCC_PLL3_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_8_16);
 LL_RCC_PLL3_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
 LL_RCC_PLL3_SetM(1);
 LL_RCC_PLL3_SetN(32);
 LL_RCC_PLL3_SetP(4);
 LL_RCC_PLL3_SetQ(4);
 LL_RCC_PLL3_SetR(2);
 LL_RCC_PLL3_Enable();
 
  /* Wait till PLL is ready */
 while(LL_RCC_PLL3_IsReady() != 1)
 {
 }
 
  /* Intermediate AHB prescaler 2 when target frequency clock is higher than 80 MHz */
  LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
 
 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
 LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
 LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
 LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
 LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
 LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_2);
 LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
 LL_SetSystemCoreClock(480000000);
 
  /* Update the time base */
 if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
 {
  Error_Handler();
 }
 LL_RCC_SetQSPIClockSource(LL_RCC_QSPI_CLKSOURCE_PLL2R);
 LL_RCC_SetSPIClockSource(LL_RCC_SPI123_CLKSOURCE_PLL3P);
 LL_RCC_SetUSARTClockSource(LL_RCC_USART234578_CLKSOURCE_PLL3Q);
 LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_HSI48);
 LL_RCC_ConfigMCO(LL_RCC_MCO1SOURCE_HSE, LL_RCC_MCO1_DIV_8);
}

The RCC is configured as follows:

HSE: Crystal / Ceramic Resonator

LSE: Disable

Master Clock Output 1: Check

Master Clock Output 1: Clear

Audio Clock Input (I2S_CLKIN): Clear

CRC_SYNC: Disable (Only have USB_FS available owing to the GPIO config)

Supply Source: PWR_LDO_SUPPLY

TIM Prescaler Selection: Disabled

HSE Startup Timeout Value (ms): 100

LSE Startup Timeout Value (ms): 5000

CSI Calibration Value: 16

HSI Calibration Value: 32

VDD Voltage(V): 3.3V

Flash Latency (WS): 4WS (5 CPU cycle)

Power Regulator Voltage Scale: Power Regulator Voltage Scale 0 (only available option)

PLL1 clock Output range: Wide VCO range (only available)

PLL2 clock Output range: Wide VCO range (only available)

PLL3 clock Output range: Wide VCO range (or MEDIUM VCO range)