Configuring GPIO threshold

[Moamen Ayman]

Posted on December 24, 2017 at 07:02

Hi everybody!

 I am working on a design using STM32F407VGT6 runs at 168MHz, I want to enable an external line interrupt with rising signal edge. I am monitoring a signal from some system which when reachs 1.3V I should consider this as high voltage and execute its ISR. After some testing I see that when MCU input signal reach 1.5v and avove(up to 3v my VDD supply voltage) it considers it as high so is there any way I can decrease this minimum active high voltage to 1.3v so I can connect to the system directly without using comparator OP-AMP and once signal reach 1.3v, MCU considers it as rising edge and execute the ISR. Is it good to decrease the system VDD to 2.6v or it will affect something else like the clock I am working on.

Thanks

[S.Ma]

Posted on December 24, 2017 at 11:01

How about ADC Analog Watchdog function? When the trigger voltage has to be precise, it's an analog function.

[Andrew Neil]

Posted on December 24, 2017 at 14:10

For digital inputs, the logic levels are fixed by the hardware, and defined in the datasheet.

What you describe is making an analogue voltage measurement, and taking a decision based on the analogue result - so, as already noted, you will need to use an ADC.

[LMI2]

Posted on December 24, 2017 at 20:22

https://learn.sparkfun.com/tutorials/logic-levels/33-v-cmos-logic-levels

 

How about lowering your power supply voltage? Power supply voltage and logic levels are related, so if you can use something close to 1.3v it might work. But not at 168MHz probably.

[T J]

Posted on December 25, 2017 at 22:35

electronically, there are 2 diode drops to trigger the switching. is about 1.1-1.3V (basically TTL)

but the tolerance is loose, it will trigger 100% approx   >= 1.0V  &  < 1.4V

Although the pin input schmitt trigger does work.(100-200mV), a comparator and a DAC would do a tighter job.