2014-09-16 08:38 AM
I'm concerned with the communication between two stm32 devices via 4-wire SPI interface, no DMA, Keil RTX.
The first device (SPI master) is a base board with stm32f427, the secind device (SPI slave) is a display with stm32f207 (both our own hardware). The second device receives the voltage supply via the first device. The problem is that the slave (display) starts up a little bit earlier (approx. 4--5 ms) than the master. This causes that the SPI interface of the slave is initialized before than the SPI interface of the master. The master sends data correctly, but these are not recognized by the slave (rx interrupt handler). If I install a small delay before initializing the slaves, then everything is working properly. Does anyone have any idea what exactly is the cause? #spi #stm322014-09-16 11:52 AM
Does anyone have any idea what exactly is the cause?
One might guess the clock is glitching, and that you enable the SPI regardless of the CS state? You'd typically put a logic analyzer on the signals, and describe those, and the data actually received at the slave, if you wanted to understand what was going on.2014-09-17 01:57 AM
Hello, clive1,
thank you for your response. The MOSI signal looks good on the oscilloscope, but the slave receives allways by 1 bit or 2 bits shifted signal. For example, 0x2D or 0x16 instead of 0x5B.Also
I see
in the debugger
that the
busy
flag
is always
set
.2014-11-04 01:37 AM
Hello Omsker
Your problem could be that when setting up the SPI master device the CLK pin change state a few times, presenting fake clocks to the slave. This will always shift the bits, and this is why the busy flag is always set. One solution could be to initialize the slave SPI interface after the SPI master is set up. You could synchronize the chips using the CS pin.