Hello @uREG and welcome to the community.
I moved your post from this one to a new thread as it's not the same question.
You can manage that in the linker file:
CM7:
MEMORY
{
FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 2048K
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
}
CM4:
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K
}
In system_stm32h7xx.c, you need to modify the vector table offset address in such way you swap the addresses between CM4 and CM7 VTOR addresses.
For CM4: (BANK1)
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
For CM7: (BANK2)
SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
And for performance purposes, in stm32h7xx_hal.c don't forget to change the ART base address according to the BANK1 address:
HAL_StatusTypeDef HAL_Init(void)
{
uint32_t common_system_clock;
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure Cortex-M4 Instruction cache through ART accelerator */
__HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
__HAL_ART_CONFIG_BASE_ADDRESS(0x08000000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 1 : */
__HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */
#endif /* DUAL_CORE && CORE_CM4 */
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