STM32H745 - Dual core

[Monish]

I have few questions on STM32H745 dual core cortex M7 and cortex M4.

i. What is the booting sequence when both the cores are enabled at the same time? Is there any application notes available in details.

ii. How both the cores uses the same resource (RAM)?

iii. How AXI/AHB bridge interconnects both the cores? Is there any registers available for the configuration?

iii. How to generate the code for the controller?

[Bouraoui Chemli]

Hi @MP.3ramanathan​ 

Please refer to application note AN5557, Figure 2 gives an overview of the dual-core system architecture.

Section 3.3 describes the dual-core boot, by default both core boot.

Also you can refer to provided templates in STM32CubeH7 package via this path STM32Cube_FW_H7_V1.9.1\Projects\STM32H745I-DISCO\Templates.

Application note AN5617 provides an overview of the dual-core communication technique.

The code can be generated using STM32CubeMX tool

[Tesla DeLorean]

>> How to generate the code for the controller?

You need to build two application, in two distinct areas of flash, notionally 0x08000000 (M7) and 0x08100000 (M4)

The FLASH, and portions of RAM are Dual Ported, there are in fact diagrams in the Reference Manual, and they also attribute memory addresses from each core there too.

[Monish]

Thanks for clearing my doubts.

How does AXI/AHB Bus bridge works to access the peripherals allocated to CPU2 by CPU1? Is there code snippet?