CAN2 Problem on the connectivity line

[plee1]

Posted on December 08, 2009 at 11:15

CAN2 Problem on the connectivity line

[plee1]

Posted on May 17, 2011 at 13:23

Hello,

I am trying to setup my CAN2 module for the STM32F105RC but unable to transmit or recieve data with the CAN analsyer. I have setup the CAN1 module the same way and it works. Is there something missing in my configuration or is there are conflict between peripherals or something? I have been looking at this problem for a while and I can't see any issues with the setup. This is causing a bit of a problem as we have several prototype PCBs using the same chipset. CAN 2 Setup

Code:

/* Enable clock for CAN2 */ RCC->APB1ENR |= (1 << 26); /* Enable clock for GPIOB and AFIO */ RCC->APB2ENR |= (1 << 3) | (1 << 0); /*Set CAN remap to use PB5 and PB6*/ AFIO->MAPR &= 0xFFBFFFFF; AFIO->MAPR |= 0x00400000; /*Setup rx and tx pin for can*/ GPIOB->CRL &= 0xF00FFFFF; GPIOB->CRL |= 0x0B800000; NVIC_EnableIRQ(CAN2_RX0_IRQn); CAN2->MCR = ((1 << 4) | (1 << 0)); // init mode, disable auto. retransmission // Note: only FIFO 0, transmit mailbox 0 used CAN2->IER = ((1 << 1) | (1 << 0)); // FIFO 0 msg pending, Transmit mbx empty /*Initialise ring buffer*/ Can2Buffer.RingBufRxCtr = 0; Can2Buffer.RingBufRxInPtr = &Can2Buffer.RingBufRx[0]; Can2Buffer.RingBufRxOutPtr = &Can2Buffer.RingBufRx[0]; /* set BTR register so that sample point is at about 72% bit time from bit start */ /* TSEG1 = 12, TSEG2 = 5, SJW = 4 => 1 CAN bit = 18 TQ, sample at 72% */ CAN2->BTR &= ~((( 0x03) << 24) | (( 0x07) << 20) | (( 0x0F) << 16) | ( 0x3FF)); CAN2->BTR |= ((((3-1) & 0x03) << 24) | (((4-1) & 0x07) << 20) | (((11-1) & 0x0F) << 16) | ((brp-1) & 0x3FF)); CAN 2 interrupt

Code:

void CAN2_RX0_IRQHandler (void) { if (CAN2->RF0R & 3) { /* message pending ? */ /*Check if buffer is full*/ if (Can2Buffer.RingBufRxCtr < 20) { Can2Buffer.RingBufRxCtr++; /* No, increment character count */ CAN_rdMsg (Can2Buffer.RingBufRxInPtr++, 1); if (Can2Buffer.RingBufRxInPtr == &Can2Buffer.RingBufRx[20]) { /* Wrap IN pointer */ Can2Buffer.RingBufRxInPtr = &Can2Buffer.RingBufRx[0]; } } else { CAN2->RF0R |= (1 << 5); /* Release FIFO 0 output mailbox */ } } }

[tomas23]

Posted on May 17, 2011 at 13:23

CAN2 is slave of CAN1, enable CAN1, too, and tell us!

[adas]

Posted on May 17, 2011 at 13:23

I have the same problem...

Did you find a solution yet ? The CAN1 interface is working OKe (send & receive) The CAN2 interface is ONLY sending, NO receive possible. Also when I use both interfaces (send from CAN2 to CAN1 --> OKe) From CAN1 to CAN2 NO receive possible. Is this a bug or what ?

[jonas23]

Posted on May 17, 2011 at 13:23

You must enable Slave filter bank in order to get Can2 rx to work.

/** * @brief Select the start bank filter for slave CAN. * @note This function applies only to STM32 Connectivity line devices. * @param CAN_BankNumber: Select the start slave bank filter from 1..27. * @retval None. */ void CAN_SlaveStartBank(uint8_t CAN_BankNumber) { /* Check the parameters */ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); /* enter Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; /* Select the start slave bank */ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; CAN1->FMR |= (uint32_t)(CAN_BankNumber)< /* Leave Initialisation mode for the filter */ CAN1->FMR &= ~FMR_FINIT; }

[adas]

Posted on May 17, 2011 at 13:23

Thanks Jonas,

Probem solved. [ This message was edited by: adas on 05-11-2009 11:18 ]

[richardandrysek9]

Posted on May 17, 2011 at 13:23

Hi I still do not know how to setup CAN2 Rx. If I understand correct to it I have to setup filters for CAN2 in CAN1 registers area? Perpahps a small example could be helpfull.

Thank you R.

[richardandrysek9]

Posted on May 17, 2011 at 13:23

Sorry that's correct. I did not see ''#ifndef''.

[richardandrysek9]

Posted on May 17, 2011 at 13:23

Is this correct in stm32f10x.h (V3.1.0)?

uint32_t RESERVED5[8]; #ifndef STM32F10X_CL CAN_FilterRegister_TypeDef sFilterRegister[14]; #else CAN_FilterRegister_TypeDef sFilterRegister[28]; #endif /* STM32F10X_CL */ } CAN_TypeDef; Perhaps it shall be so: uint32_t RESERVED5[8]; #ifndef STM32F10X_CL CAN_FilterRegister_TypeDef sFilterRegister[28]; #else CAN_FilterRegister_TypeDef sFilterRegister[14]; #endif /* STM32F10X_CL */ } CAN_TypeDef;

[armmcu]

Posted on May 17, 2011 at 13:23

Hi Richard,

I can find this in ST documentation (reference manual :connectivity line product) ''- CAN1: Master bxCAN for managing the communication between a Slave bxCAN and the 512-byte SRAM memory. -CAN2: Slave bxCAN, with no direct access to the SRAM memory.'' Hence when using CAN2 it's obligatory to enable the Clock of CAN1 accordingly. that's all ;) One more point you have to take into account that for CAN2, filter number starts from 14 to 27 by default. CAN2 filter can also start from another bank number using the following function from the STM32 library from ST: CAN_SlaveStartBank(uint8_t CAN_BankNumber); may this help :-] Cheers, ARMCU.