CAN wrong bit timing

[HiSt]

Hello together,

i had a problem with setting a correct bit time on a CAN-port.

On my nucleo-h755ZI-Q board, I want to operate the FDCAN1 by the CM4 in classic-can mode with a baud rate of 1 MHz.

I supply the FDCAN with a clock of 50MHz:

Therefore the corresponding registers are set as follows:

With:

this excerpt in the reference manual, the calculation is:

tfdcan_tq_ck = 0,02 µs  <- (1/50MHz)

tq = 0,1µs          <-             (0,02 *  5)

The bit time ist 1µs   <-  (0,1 *( 7+1+0+1+1))

-> baudrate is 1 Mhz    -> 1/1µs

But in the outgoing frames, I measure a bit time of approx. 3µs.

Enlarged:

How can that be? What did I do wrong or overlook?

Thank you and best regards,

HiST

[STuser2]

Was the CAN communication established between the two nodes at 1Mbps? Were you able to receive and transmit messages? Just for confirmation.

[HiSt]

No, due to incorrect bit timing and the resulting incorrect baud rate, I cannot communicate with another participant.

[mƎALLEm]

Hello,

Attach your ioc file and tell more about what you are connecting to nucleo-h755ZI-Q as a second CAN node.

[STuser2]

I don't think it is the correct method to measure the bit timing without establishing communication, there shall be at least one other node to acknowledge the message.

[HiSt]

Hello m3ALLEm,

Here is a sketch to illustrate this:

Best regards,

HiST

[HiSt]

Hello STuser2,

There is another node that is not responding. The measurement should show at least one bit with the correct time.

I also have a logic analyzer that cannot interpret the signal from the FDCAN1.

Best regards,

HiST

[mƎALLEm]

Ok thank you for the sharing.

According to your ioc file:

1-  The FDCAN clock source is generated from an external crystal which is OK.

2- The bitrate is set at 1MHz which is correct.

3- Better to increase the FDCAN clock and increase TSeg1/Tseg2 values with a sampling point positioned at ~87.5%. Therefore, I recommend the following config:

FDCAN clock source = PLL1Q = 80MHz:

and CAN bit time (sample point set at 87.5%):

[mƎALLEm]

Just forget that you are using a nucleo-h755ZI-Q while in the Clock config you set the crystal to 25MHz in a crystal mode! But there is no external crystal in that board connected to OSC_IN/OSC_OUT.

This is the schematic:

What I suggest is to use the bypass mode but for that you need some steps:

1- Modify the STLINK MCO output to generate 5MHz instead of 8MH generated from HSI. Ensure SB72 is soldered. Please refer to this article to do that: How to use STLINK-V3 MCO output on Nucleo boards as a precise clock source for STM32

How to use STLINK-V3 MCO output on Nucleo boards as a precise clock source for STM32

2- In your ioc file you need to update the RCC config: HSE in Bypass mode with HSE value = 5MHz

+ use the same bit timing config I provided in my previous post.