Can Bus, sending and receiving does not work

[csminus]

Posted on June 15, 2015 at 21:25

ghhhhhhhhhhhhk

#lmgtfy #can-bus #stm32f207 #can-prescale-and-quanta

[Tesla DeLorean]

Posted on June 18, 2015 at 20:19

May be it's not the software? Step back, and think about how you're tackling and presenting the problem.

Document/diagram your board and connectivity, along with your test methodology and scope traces.

[csminus]

Posted on June 19, 2015 at 09:11

w was checked can i device with oscilloscope and its sending something on PA11 and PA12, im using can converter i-7530 connected to PC, soo i cant check ESR reg on it, i can check it only on me device

[csminus]

Posted on June 19, 2015 at 10:14

i just check and i have  Bit Dominant Error - 0x50, when i set prescaler <= 16 i have

Acknowledgment Error - 0x30

[Tesla DeLorean]

Posted on June 19, 2015 at 13:29

Then you should perhaps focus on getting some coherent baud rate settings. In the last code pasted that looked to be 31250 baud, based on the limited data I'm working with here.

[Tesla DeLorean]

Posted on June 19, 2015 at 13:33

For a 250Kbit/sec data rate I calculate the prescaler as:

clock = 120000000 / (1 + 6 + 8) = 8000000  (CAN clock ticks, sum of quanta)

prescale = clock / rate = 8000000 / 250000 = 32 Not clocking at 120 MHz

[csminus]

Posted on June 19, 2015 at 13:34

ok i will try it and write post ;] thx

[csminus]

Posted on June 19, 2015 at 13:43

I set prescaler like in your post 32 its to much?

[Tesla DeLorean]

Posted on June 19, 2015 at 13:58

I was responding to Jack's values....

For 250 kbps I'd use a prescaler of 8, presuming a 30 MHz APB1 (CAN) clock, and 15 time quanta

[csminus]

Posted on June 19, 2015 at 14:09

eh i try almos all prescalers and still nothing, maybe its converter problem but i cant check it i think

[csminus]

Posted on June 24, 2015 at 08:31

his file configures the system clock as follows:

  *=============================================================================  *=============================================================================  *        Supported STM32F2xx device revision    | Rev B and Y  *-----------------------------------------------------------------------------  *        System Clock source                    | PLL (HSE)  *-----------------------------------------------------------------------------  *        SYSCLK(Hz)                             | 120000000  *-----------------------------------------------------------------------------  *        HCLK(Hz)                               | 120000000  *-----------------------------------------------------------------------------  *        AHB Prescaler                          | 1  *-----------------------------------------------------------------------------  *        APB1 Prescaler                         | 4  *-----------------------------------------------------------------------------  *        APB2 Prescaler                         | 2  *-----------------------------------------------------------------------------  *        HSE Frequency(Hz)                      | 25000000  *-----------------------------------------------------------------------------  *        PLL_M                                  | 25  *-----------------------------------------------------------------------------  *        PLL_N                                  | 240  *-----------------------------------------------------------------------------  *        PLL_P                                  | 2  *-----------------------------------------------------------------------------  *        PLL_Q                                  | 5  *-----------------------------------------------------------------------------  *        PLLI2S_N                               | NA  *-----------------------------------------------------------------------------  *        PLLI2S_R                               | NA  *-----------------------------------------------------------------------------  *        I2S input clock                        | NA  *-----------------------------------------------------------------------------  *        VDD(V)                                 | 3.3  *-----------------------------------------------------------------------------  *        Flash Latency(WS)                      | 3  *-----------------------------------------------------------------------------  *        Prefetch Buffer                        | ON  *-----------------------------------------------------------------------------  *        Instruction cache                      | ON  *-----------------------------------------------------------------------------  *        Data cache                             | ON  *-----------------------------------------------------------------------------  *        Require 48MHz for USB OTG FS,          | Enabled  *        SDIO and RNG clock                     |  *-----------------------------------------------------------------------------  *=============================================================================  ******************************************************************************I find it in system_stm32f2xx.h its normal settings?