Posted on June 28, 2018 at 15:32Dear colleagues,
Could you please help to understand CAN 'bus-off' operational in a correct way? (can not find a proper description in the Reference manual for STM32F4).
Some assumptions
a) Suppose that ABOM bit in the CAN_MCR register bxCAN was set (The Bus-Off state is left automatically by hardware once 128 occurrences of 11 recessive bits have been monitored). Suppose that at the end of the time-periodic cycle (10ms) I send CAN-frame. Also, NART (No-Automatic retransmission bit) was set to 0 (i.e. the CAN hardware will automatically retransmit the message until it has been successfully transmitted according to the CAN standard).
b)Suppose I get some failure on CAN-bus, and can not transmit anymore via CAN, before I send my next CAN-frame at the end of 10ms cycle.
Now the questions
1)Is it correct that after I load my frame into CAN-transmit register at the end of 10ms cycle I will get 'error bus-off interrupt' after 255/8 attempts to send this frame(TEC reach 255)?
2)Is it correct that at the end of the next 10ms cycle when I again will try to load my frame into transmit register I will get 'error bus-off interrupt' immediately (TEC already 255)? Will I get this 'error bus-off interrupt' every time I will try to load frame into transmit register while bxCAN in the bus-off state? Is it correct that this BOFF from CAN error status register remains set all the time while bxCAN in the bus-off state (TEC=255)?
3)Suppose that this failure on CAN-bus somehow faded, and I receive this 'recovery sequence' i.e. bxCAN now does not in the 'bus-off' state. Will it mean that TEC is reset to 0 by hardware? Will it mean that BOFF from CAN error status register is reset to 0 by hardware? Will I get normal transmit interrupt in the case of attempt to load some frame into CAN-transmit register?
