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Busfault when reading device unique id on stm32h7b3

aco990
Associate III

Hello everyone,

i am trying to read the device unique id of my stm32h7b3 mcu, but get a bus fault on line 2:

 

 

  uint8_t* uid_base = (uint8_t*) 0x08FFF800;
  uint8_t i =  uid_base[0];

 

 

aco990_0-1719915957217.png

Do you know what could be the problem ?

1 ACCEPTED SOLUTION

Accepted Solutions
SofLit
ST Employee

Hello,

Getting back with analysis of the behavior. 

In fact the behavior is expected with STM32H7B/A devices (not the case of STM32H74x/5x/2x/3x), and this is described in the RM0455 / "Single read sequence" section:

SofLit_1-1731936694855.png

Since the UID is located at the address 0x08FFF800 accessed by the CPU over AHB, it could not be accessed with byte but with half-word or word.

From RM0455:

SofLit_2-1731937038744.png

And in your example you're accessing the UID with bytes:

  uint8_t* uid_base = (uint8_t*) 0x08FFF800;
  uint8_t i =  uid_base[0];

 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

View solution in original post

7 REPLIES 7
aco990
Associate III

If i change the pointer to uint16_t* i can read without hardfault. But The reference manual says bytewise reading is possible. What do i wrong? On the stm32h743 i can read it bytewise.

@STOne-32 , @Peter BENSCH 
Best regards

Hello @aco990 ,

I reproduced the behavior on stm32h7b3 and not on STM32H743.

Question: did you enable the data cache? in that case are you facing the same behavior?

 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

The issue is only on the stm32h7b3. The stm32h743 is working fine 

No the data cache is not enabled on both mcu

Hello,

My comment was to test with Dcache enabled. Do you have the same behavior or not?

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

Hello @SofLit ,
why  should i enable the data cache? On the stm32h743 it is working without data cache enabled.

Best regards

why  should i enable the data cache? On the stm32h743 it is working without data cache enabled.

The idea was just to run a test.

Sorry if you are not cooperative we cannot help you efficiently. 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
SofLit
ST Employee

Hello,

Getting back with analysis of the behavior. 

In fact the behavior is expected with STM32H7B/A devices (not the case of STM32H74x/5x/2x/3x), and this is described in the RM0455 / "Single read sequence" section:

SofLit_1-1731936694855.png

Since the UID is located at the address 0x08FFF800 accessed by the CPU over AHB, it could not be accessed with byte but with half-word or word.

From RM0455:

SofLit_2-1731937038744.png

And in your example you're accessing the UID with bytes:

  uint8_t* uid_base = (uint8_t*) 0x08FFF800;
  uint8_t i =  uid_base[0];

 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.