Showing results for 
Search instead for 
Did you mean: 

BiSS-C Implementation

Associate II

Hi All,

we are evaluating the possibilty to use a BiSS-C encoder in our project. First time using BiSS-C.

From the BiSS-C standard it seems to me that BiSS-C can be implemented at STM32 level by mean of an SPI peripheral connected to an Rs422 transceiver.

Things that is bugging me is that BiSS-C frame seems to not be aligned to 8-bit boundary (e.g. to transfer 26-bits exactly 26 clock pulses have to be yielded) so SPI cannot be fit for this application.

Does anyone already implemented BiSS-C interface with STM32? How to?

Thanks in advance for your support,



Which STM32, there's hundreds, some support alternative bit lengths.

The F7 should support 13-bit words, so two words would clock 26-bits.

Others yes, you'd probably need to bit-bang the interface to get quirky counts, or find some least common denominator

Tips, buy me a coffee, or three.. PayPal Venmo Up vote any posts that you find helpful, it shows what's working..
Andrew Neil
Principal III

It's not that uncommon for SPI masters to be restricted to multiples of 8 bits so, presumably, the same problem must exist beyond STM32?

Are you sure that extra clocks are strictly not allowed?

Could you look at using a USART in sync mode?

What does the encoder manufacturer suggest?

As @Community member​ says, bit-banging gives you ultimate control...

Associate II

Hi All,

thanks for the answers.

The target uC is STM32G474RE but, as pointed out by @Andrew Neil, it's rather common that SPI yield data aligned to 8-bit boundary.

Extra Clock pulses cannot be fed to encoder device (at least as last as I've understood) and the manufacturer doesn't suggest anything since it specifies to comply to BiSS-C interface (and that's all).

The issue is present also with other Silicon Vendor (exception done Texas Ins.) but we intend to use STM32 to reuse code from previous projects and also for strong knowledge base that we built up during those years.

Does a reference design for BiSS-C interface is available for STM32?

Thanks again for your support,


Maybe BiSS Association can help?

Seems that many are using FPGA, and interface chips are available:


I found a good solution to read BiSS-C/BIS3 packets over a SPI bus. In my case I am reading 30 bits from a Zettlex Inductive Encoder into a Nucleo-G474RE STM32 development board. The Reference Manual (RM0440 Rev 7) has a subsection in section 39.5.9 called "Sequence Handling" that mentions how to get the clock to run as long as you need until you get any number of bits that you want:

"In receive-only modes, half-duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0, RXONLY=1) the master starts the sequence immediately when both SPI is enabled and receive-only mode is activated. The clock signal is provided by the master and it does not stop until either SPI or receive-only mode is disabled by the master. The master receives data frames continuously up to this moment."

I set my data size to 8 bits. I call HAL_SPI_Receive(&hspi, pdata, 6, 1000) to receive 48 bits (just needs to be more than 30 bits). Now can I parse through the returned pdata array and pull out the data bits, nE/nW bits, and CRC bits as I need them. See the included Logic Analyzer image to see how the data is the same no matter if it's analyzed as BiSS-C or SPI. Just needs to be a bit massaged (pun intended).

_legacyfs_online_stmicro_images_0693W00000bi3MpQAI.pngGood luck!


Reference Manual for STM32G4:


I am doing a project with BISS-C to read the position. Are you willing to share your code?