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Basic timer questions STM32L476?

SWenn.1
Senior III

‎2023-01-21 06:28 AM

Hello all...

Can someone give me direct answers below...(And please don't refer me to documentation as I have scoured thru it and not solved my questions)

I would like some clarity as I have found no documentation to clarify the following:

  1. When using compare output and pwm for triggering other timers does RCR have any affect? or does RCR only affect UG?
  2. When a timer is configured to use ITRx and in slave mode and NOT External Clock Source does the timer automatically just use the internal clock source?
  3. I have yet to find the value of TG in EGR as no one has taken the time to show a Figure wrt to this topic....Can anyone tell me it's value?
  4. I cannot make heads or tails from what ST is trying to say in the UM Figure 376....What are they trying to show here? CNT_INIT??? this is the only place in the whole RM this is mentioned. The paragraph before the figure is almost as incomprehensible....UG signal here doesn't seem to align with anything going on within the figure???
  5. Finally UG and TG.....what are their value? Doesn't everyone use interrupts? in particular the Update Event in Trigger Selection, is this tied to UG????

ST documentation is very poor with respect to labeling and consistency. They could do a whole bunch better if they stuck with using the register names and bit field names throughout their documentation especially on figures......

Sincerely

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Danish1
Lead II

‎2023-01-23 02:29 AM

I think your questions are not basic, but instead relate to advanced features of the timers. And it wouldn't surprise me if none of the HAL examples cover such advanced features. I'm disappointed no-one who uses these features has chipped in; in the absence of anything better I'll give my thoughts.

I find the Reference Manual RM0351 the best we have, and I'm grateful for it. There are areas where it isn't clear, and only then do I reach for examples or experimentation.

  1. Fig 223 implies RCR only affects Update generation and Update Interrupts.
  2. That's what I'd expect. Experimentation might clarify this.
  3. Section 30.4.6 seems to show this. Have I missed something?
  4. Section 33.3.4 refers to this figure. I guess whet they're showing is when writing to CEN and/or UG actually take effect. My thinking is that CEN gets the counter counting (again). And UG is what triggers the CNT_INIT internal signal which causes the counter-register to be reloaded.
  5. Yes I think UG is a manual event you can fire when convenient to get the timer going.

Hope this helps,

Danish

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SWenn.1
Senior III

‎2023-01-23 06:18 AM

Thank you for your response....As a HW engineer I want to know all the nuances of how this operates bcz many times that helps me make decisions on which processors to use for a given design job. I am coming from a TI background and those are extreme low power devices where you need to know all the details and code is written, many times, as bare metal to "eek" out the lowest energy. I feel most ppl who use STM are happy with the HAL stuff and don't require to understand the low level detailed operation as their application can get away with drawing a few more mA's here and there....As a newbie to this architecture I rely heavily on the details of the manuals and it is very frustrating to have inconsistent information in these documents. I wish documentation was tighter.....

PS.....Trust me I have been doing much experimentation :)

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