Backup SRAM for persistent RAM

[ssmail]

Posted on May 24, 2016 at 23:31

I am using an STM32F4 for a project that undergoes in-field upgrade. The upgrade involves a soft reset, but I would like to back-up some critical data that will ‘persist’ through the upgrade.

Since the data that needs to persist is updated at least once a second, I would like to use persistent RAM (rather than Flash). I was considering using the Backup SRAM described in RM0090 section “5.1.2 Battery backup domain�? for this purpose.

Assuming I have all access to this memory occur within the same thread, are there any concerns with using Backup SRAM in this way.

e.g. Is there an issue with writing to this memory many times a second by executing the code below?

</p>

        // Enable Power clock

</p>

        __PWR_CLK_ENABLE();

        // Enable access to Backup domain

        HAL_PWR_EnableBkUpAccess();

        {

               uint32_t u32NVData = GEtTestData();

               RTCWriteNVDataWord(0, u32NVData);

        }

        __PWR_CLK_ENABLE();

        // Enable access to Backup domain

        HAL_PWR_EnableBkUpAccess();

Note: I do not have a battery to power this RAM. Losing contents upon power-down is acceptable.

[Tesla DeLorean]

Posted on May 25, 2016 at 00:18

Regular SRAM is also retained across a reset, it is the C runtime/startup code that will mess things up. You can create a hole in the linker script/scatter file to remedy this.

The Backup RAM will be fine without a battery across a reset.

[ssmail]

Posted on May 25, 2016 at 17:11

Thanks clive1.

Maybe it would be easier to modify the

 linker script/scatter file, then the enable/disable calls would not be necessary.

I'm considering using NOINIT Compiler DirectiveAs described here:  

http://www.keil.com/support/man/docs/c166/c166_noinit.htm

Are there any Caveats to doing it this way?