APB Timers can exceed the APB domain max clock ?

[zeros_and_ones1991]

Posted on February 12, 2015 at 16:57

I have STM32F429I chip , I want to used timers , at the same time im running the APB1 at its max speed of 45 MHz . Now the clock provided to the APB1 timers will be double the clock of the APB1 domain by hardware . Is that safe ? 

[Tesla DeLorean]

Posted on February 12, 2015 at 17:17

Is that safe ?

It's a fundamental part of the STM32 series design. The timers were carefully designed, with a number of the hazards in mind and addressed. The incrementer/decrementer is certainly capable of 16-bits @ 180 MHz, and 32-bits @ 90 MHz, and that's likely to be the main critical path.The APB clocks are typical HALF what goes to the TIMCLK, except for the DIV1 cases. There is likely a single divider chain, and your clocks are multiplex from that. They are all synchronous, so should have no clock boundary issues unless you purposely invert the clock priorities, ie set APB1 > APB2 for instance. The phase relationship won't change.

[zeros_and_ones1991]

Posted on February 12, 2015 at 17:29

thx clive for ur reply , but what u mean by Critical path ? 

That confused me , so the qs is still , Is that safe?

[Tesla DeLorean]

Posted on February 12, 2015 at 18:36

A Critical Path is the one which introduces the most delay/latency in the design, and ultimately limits the upper frequency at which the design, or portion thereof, can be clocked. ie Long chains of flip-flops and combinational logic that depend on things like carry propagation, where the next state depends on something that is in the midst of evaluation. So counters and adders. If the critical path takes >~100ns you can't clock at >=10MHz

Is that safe? What does that actually mean in this context? I wouldn't leave my child alone with it. I wouldn't ingest it, or be using bit-banding on the status register.

[zeros_and_ones1991]

Posted on February 12, 2015 at 18:47

By safety I mean it wont cause any hardware to heat up .

That 's is not clear in the User manual , when they speak about the Max. freq , it's not clear whether they mean exceeding this limit , the chip wont function properly  , or they mean the hardware might heat up . 

[Tesla DeLorean]

Posted on February 12, 2015 at 20:50

The speed limits are primarily where the hardware malfunctions over the temp/voltage profile.

Higher clocks will draw more power, and heat things up more, I'd be worried more about the counters and math units in the processor. The TIM units aren't particularly complex, allowing them to clock faster than more complicated units. Having the TIM clock at a higher rate is advantageous, the faster they are the more useful/flexible they are. Think of the maximum clock as how fast you can move your legs while running, and not falling over. It doesn't do any damage to just violate the critical path.