ADF clock constraints

[nicolas]

In the example ADF_AudioRecorder, the OutputClock.Divider is set to 4 (STM32Cube_FW_U5_V1.7.0\Projects\STM32U575I-EV\Examples\MDF\ADF_AudioRecorder\Src\main.c).

But the datasheet RM0456 at page 1610 say: Fadf_proc_ck > 4 x FADF_CCKy

With Fadf_proc_ck = 4 x FADF_CCKy, this example doesn't respect the clock constraint.

Who is correct ? the example or the RM ?

[Imen.D]

Hello @nicolas,

Thank you for having reported this.

This will be escalated internally (via Internal ticket number: 211868) for analysis and I will be back to you with update.