ADC sampling of continuous signal starts at different time due to jitter

[mgb]

I need to sample a continuous analog stream of 2 ramp signals using the STM32WB15CC MCU. The ramps are generated by another IC but are disciplined by the rising edge of a PWM generated by TIM1. The analog inputs are connected to ADC_IN5 and ADC_IN7 respectively.

I have configured the ADC in scan mode single conversion and every conversion sequence is triggered by another timer TIM2 which has a TRGO Update generated every 500 kHz. I want to sample every ramp at a specific sampling rate (in this case 500 kHz) and I previously know the ramp duration, so i know the number of samples that a ramp needs and can use DMA to process a buffer when all the samples from one ramp have finished acquisition.

Right now, as the ADC is not in continuous mode, I need to enable the ADC every time the samples from the ramp have finished aqcquiring and in an ISR for the PWM I use HAL_Start_ADC_DMA but I have seen this introduces a random variable delay until the ADC starts sampling which introduces a random jitter of the start time, making the sampling of the ramps unaligned to the PWM trigger. If I just keep sampling and don't stop & start the ADC, an overrun is caused. How could I perform a sampling of a continuous signal and then process it? I have attached a picture diagram of what I want to achieve.

[MasterT]

It's not clear what error you have. Simply run adc in continuous mode with dma -circular. I 'm not sure 64MHz uCPU could meaningfully digest 500 ksps samples or what ever dsp involved

In summary, to have system synchronous, I'd set adc in free-run mode adjusting internal ADC clock divider or S/H timing to get sampling rate close to desired value, 500 ksps or so. Than dma-> mem. Timer to trigger ramp, has to be in slave mode to your sampling rate, it should not be too difficult to set - use system clock divider calculated based on adc dividers.