ADC reading on STM32H7B0 CPUs

[User16676492070816115843]

Hi!

I am having problems reading accurate values using the STM32H7B0 CPU. I have identical boards with STM32H7A3 and STM32H7B0 CPUs and the results from the B0 boards are off by a lot. I have also tried to run the ADC in 12 vs 16 bit mode and the scaled results differ quite a bit. When I run the same test on the A3 board, the results are accurate.

Does anyone else have any experience with the ADC on the H7B0 CPU? I have tried to find any differences in the datasheets but I cannot find any major differences that would impact the ADC performance

[RomainR.]

Hello @User16676492070816115843 (Community Member) 

This assumes that your hardware is made by yourself.

Both devices have exactly the same ADC, so they should get the same performance.

Can you give more information about the differences you see, what are your analog sources, what is source impedance compared to ADC sampling time? Do you incorporate filters between the STM32 and your analog sources?

What is your firmware setup in 12b and 16b?

ADC frequency and VDDA/VREF configuration ?

Do you perform an autocalibration of the ADC offset and did you try with know static analog signal to compare ?

Let me know.

Best regards,

Romain,

[User16676492070816115843]

Hi!

Thanks for the input! I just spent a little more time checking the layout and I noticed that the VSSA and VREF- pins got disconnected from the GND plane when I generated the final gerber output :( Up until now I have only been double checking the VDDA and VREF+ routing. Thanks for confirming that the ADC structure is identical in the different variants of the chip.

I just ran a test where I generated input voltages ranging from 0.5V all the way up to 1.5V and the response curve is super linear, but it intersects 0V (ADC reading) @ -0.6V

My guess is that the floating GND pins are getting biased through the substrate of the chip, as the difference is more or less a diode drop.

Obviously, this is something that the chip cannot accommodate for but since we already built 1k+ boards with this bug, I understand if you cannot go into the details of the analog structure of the chip, but does it make sense to you that the offset that I am seeing is from a diode drop? We have fairly accurate calibration in our production line, so my working assumption right now is to see if I can calibrate this to avoid having to scrap 1k boards + chips.

Best regards,

Stefan

Y = measured value from the ADC, calculated from VREF+ set to 1.8V

X = input voltage applied using a bench supply

[RomainR.]

With such hardware conditions VSSA and VREF- physically disconnected from GND, I doubt you can guarantee a normal operation of your product and even less compensate this offset of -0.6V by a calibration. This seems to me to be a bad starting point :\

Best regards,

Romain,

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