ADC in Cortex M3

[ashutosh]

Posted on October 04, 2009 at 12:42

ADC in Cortex M3

[ashutosh]

Posted on May 17, 2011 at 13:25

Hello

I am using ADC interrupt in my project. For that i have to use 2 ADC channels and read the respective value in ADC interrucp (EOC = End of Conversion) after defined period. I have configured the ADC but after interrupt generated my firmware can't return to main function and all functions stop executing further. So anybody can suggest me what to do in ISR of ADC. Thanks

[picguy]

Posted on May 17, 2011 at 13:25

All Cortex-M3 ISRs exit in the same way as normal subroutines. Indeed, other than having its address in the proper vector the compiler need not know that your ISR subroutine is an ISR. I.e. to exit simply return. (Or bx lr in assembly.)

The C compiler will save and restore any r4-r11 used in any subroutine. In assembly code you are responsible for preserving r4-r11. This is the rule for both C-called subroutines and ISRs as well. The ISR process puts a funky value in lr which makes bx lr selecting the proper return stack and processor state then restore r0-r3, r12, xPSW, the original LR and PC. There is nothing special about ADC interrupt processing that is not common to all interrupt processing. Other than any specific ADC actions. Does your ISR appear to hang? Most ISR processing must reset the condition that caused the ISR or the ISR never exits.

[st3]

Posted on May 17, 2011 at 13:25

Quote:

Most ISR processing must reset the condition that caused the Interrupt or the ISR never exits.

I don't know about ''never exits''; but it could certainly mean that the ISR would be re-started immediately it exits - which would have pretty much the same effect of making the system appear ''hung''...

[ashutosh]

Posted on May 17, 2011 at 13:25

Exactly,if the ISR of ADC will reset the condition and continuously the ISR will execute then there will definately be problem of hung...

So i am attaching the code of ADC config and related ISR for better understanding. If anything wrong in declaration then kindly discuss. Thanks

[picguy]

Posted on May 17, 2011 at 13:25

My entire TIMER3 ISR:

TIM3 ldr r0,=baseTIM3 movs r1,#0 ;tell the timer we saw its int str r1,[r0,#TIM_SR] ldr r0,=msCount ldr r1,[r0] adds r1,#1 ;1KHz count++ str r1,[r0] bx lr ;done Zeroing TIM3_SR clears the UIF (bit 0.) The UIF flag is set when the timer reaches its count. UIF also keeps the interrupt active. (Because in my application all other bits are okay to be zero I simply zeroed the word.) From the register description: The UIF bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: If I failed to reset UIF then when I exit with bx lr the interrupt will still be active. The ISR will be entered again. Instead of counting up one every millisecond I will stay in the ISR counting up at over 1 MHz – and never getting back to my mainline.

[ashutosh]

Posted on May 17, 2011 at 13:25

I have cleared the pending Interrupt flag in the ADC 1 ISR routine.

but the problem still arises. I have uses the seperate registers to reset the flag instead of API. is there any other flag to cleared or any other reason. PLS confirm. Thanks

[16-32micros]

Posted on May 17, 2011 at 13:25

Hi,

You should clear the ADC pending bit using ADC_ClearITPendingBit() function in your ADC routine, Could you also check if the sleep-on-exit feature has been enabled in your application ? If yes, the sleep-on-exit feature would put the Cortex-M3 into sleep mode after the handler exit. Hope these pointers help you. Cheers, STOne-32.