ADC1 problem with 3 channels through interrupt

Posted on May 17, 2011 at 13:25

I liked the way Luminary Micro did its Cortex-M3 ADC. (Max 8 channel setup with separate h/w result registers & interrupt possible on any channel.) I got so confused with the STM32 ADC I used injected channels only. This worked for me because I had a max of 4 analog inputs.

If my project ever gets funded I will likely recast my code to use regular channels and DMA. An interrupt after the last of 4 channels is converted and DMA’d to RAM would work for my application. All I need is 8 KHz on each of 4 channels.

Oh yes, you had a question. If you are doing one channel at a time the DMA channel is the one you put into SQ1 (the low 5 bits of ADC_SQR3.) But then if that were the case you were not likely to ask here.

Changing your approach may work well. You might consider setting your 3 ADC channels to DMA 3 words into RAM and then interrupt. In your ISR restart your ADC. Keeping your ADC / DMA running as fast as possible leaves an always recent ADC value for each channel in RAM.

Posted on May 17, 2011 at 13:25

Dear All,

I'm using my own design board with the STM32F103RBT6.

I configured my ADC1 to hold group of three channels in regular mode.

If ADC1 End-Of-Conversion interrupt (EOC) was generated, how can i know which one of the three channels, ADC1 data register relates to?

Thanks.