About branch prediction of STM32H7(Cortex-M7)

AFAIK details are not public.

I would be surprised if this would go beyond remembering result of the last or last few branches and assuming they will go the same way again. This is a good strategy e.g. for basic for loops.

JW

https://www.st.com/content/ccc/resource/training/technical/product_training/group0/84/37/18/81/04/b7/40/b3/STM32F7_System_Core/files/STM32F7_System_Core.pdf/jcr:content/translations/en.STM32F7_System_Core.pdf

One might surmise that it prefetches from potential branch targets, and pipelines speculative execution, so that if it mis-judges the flow there's only a single cycle cost rather than a full pipeline cost.

https://developer.arm.com/documentation/ddi0489/b/system-control/register-descriptions/auxiliary-control-register

Thank you for your answer.

>if it mis-judges the flow there's only a single cycle cost rather than a full pipeline cost.

->Do you recognize that even if you misjudgment the flow, the branch processing time will be very short because it will be a single cycle cost?

Thank you for the document.

Please tell me how to set the Axial Control Register (ACTLR) to use branch prediction properly.

https://developer.arm.com/documentation/ddi0489/b/system-control/register-summary

https://developer.arm.com/documentation/ddi0489/b/system-control/register-descriptions/auxiliary-control-register

Branch prediction is enabled by default and you don't have to do anything.

P.S. How can "Auxiliary" be read as "Axial"?