8 Byte stack align in interrups (vs. 4 byte)

[sholojda]

Hi. I realize this may seem simple to some of you but i realy want to undestand this as easy as it is possible.

In STM32 (for example) there is a bit called STKALIGN. If this bit is set stack is align to 8 byte instead of 4 byte.

How can i see difference in behavior when this bit is set or not? How to use this?

I know wthat align is but it is hard to undestand if i do not see how it works.

[Pavel A.]

See here to understand why it is needed:

https://community.arm.com/developer/ip-products/processors/f/cortex-m-forum/6344/what-is-the-meaning-of-a-64-bit-aligned-stack-pointer-address

How it works:

Assume that interrupt strikes just after the program pushed a word on the stack, so the stack is not 8 bytes aligned.

To align the stack for the handler, hardware automatically pushes one more word as part of "stacking" procedure, and sets bit 9 of the saved PSR to remember this.

On exit from the handler the stack is automatically restored.

The fine manual to read is PM0253. Enjoy ))

--pa

[sholojda]

Hi.

I read this couple of times trying to understand this. But that raised even more questions :)

How can i see this is needed?

How can i see this work?

[Pavel A.]

Hmm... perhaps read it another time?

[Radosław]

Probably this will be hard to obserwe. But when stack isn't 8byte aligned and in interrupt some 64-bit variable will be allocated on stack, then will be a problem. but chance for this is low and effect is unpredicted.

[Pavel A.]

This is trivial to observe: 1.when SP is aligned on 8, push a word. Now SP is not aligned on 8. 2. Cause an interrupt, SVC for example

--pa

[Radosław]

forcing this without any efects isn't an observation.

[sholojda]

So Pavel i took yours clever advice, I've looked there one more time andto my surprise nothing more appeared. No more example explaining how it works. What is benefit of this 8 byte align. How can i use it.

[Tesla DeLorean]

The Cortex-M parts people are discussing here don't have the 64-bit data paths that would be an issue for LDRD/STRD and LDM/STM against 32-bit aligned addresses.

I don't recall VPUSH/VPOP being an issue.

Alignment and data access The following data accesses always generate an alignment fault:

• Non halfword-aligned LDREXH and STREXH

• Non word-aligned LDREX and STREX

• Non word-aligned LDRD, LDMIA, LDMDB, POP, LDC, VLDR, VLDM, and VPOP

• Non word-aligned STRD, STMIA, STMDB, PUSH, STC, VSTR, VSTM, and VPUSH

[Tesla DeLorean]

It is for architectures where the data paths, busing, or memory subsystem have 64-bit paths, and where additional time penalties will occur when transactions are split.

The ABI recommendation is for cross-platform harmony and ease of porting.