2015-07-22 02:24 PM
Hi. I have another question... :)
I use STM32F103c8 MCU and it has only 16-bit timers. I need a 32-bit timer with high resolution (72 MHz). I made it with connecting two 16-bit timers (one as master, second as slave). Master is counting with 72 MHz, while slave increments on a master's overflow. Both of them are in (IC) Input Capture mode. I latch their CNT registers with a pulse on one GPIO pin, which is connected on both IC channels. Than I read both CCR registers and make a 32-bit value. That works perfectly, if I reduce master's frequency a lot (with prescaler). But with full speed, some strange things occasionally happen around master's overflow... If I latch them when master is just above the overflow (few counts over 0), slave still don't update his value by 1 (its value is still old - for 1 smaller than it should be). Thus, when I combine both values, I get for about 2^16 smaller value than I should.Now I solve this problem by software. When I need a value, I make two consecutive readings. If the second one is just for a little bit larger than the first one, then I'm sure that the second reading is true. It works...But, I would like to ask, if anyone had the same experience when combining two 16-bit timers into 32-bit? Am I doing something wrong here?Thank you in advance. #timer #stm32f1032015-07-23 07:31 AM
Since two capture register reads are required, there is a finite time in between when a master overflow can occur. The workaround is probably the answer.
Cheers, Hal2015-07-23 10:09 AM
16-bit timers, and poor clocking strategies have long frustrated me in the STM32 designs.
Do you have a compelling reason to be using an STM32F1 part over one of the newer versions of the part? One that has 32-bit timers, although on the slower APB1 bus.2015-07-23 11:03 AM
Because it is cheaper than newer MCUs and it has smaller footprint. These are the main reasons.
2015-07-23 02:34 PM
Even some STM32F0 parts have one 32-bit timer.