Trying to skip PWM outputs upon low modulation (STM32F405)

[pf26]

I am using 3 Channels to generate 6 pwm using complementary pwm by timer 1. I want to release outputs of CH1 and CH1N when modulation is low (ie. PWM near 50%), and do the same for other channels (shifted 120degrees in time).

I try playing with register CCER :

TIM1->CCER &= TIM1_OC1_DISABLE;  // using  #define TIM1_OC1_DISABLE ((uint16_t)0xFFFE)

and later :

TIM1->CCER |= TIM1_OC1_ENABLE;   // using #define TIM1_OC1_ENABLE ((uint16_t)0x0001)

Disabling works fine, but re-enabling is done with approx 10ms delay for some reasons when I need a few tens of us max delay.. (PWM is at 30kHz, center aligned)..

Using MOE bits works fine, but does skip outputs on all channels simultaneously.

Any idea ? Thks, Pierre

[AScha.3]

I cannot imagine, why dis-/enable should have a big delay - except, there is no "update" event.

(You writing values to the shadow registers, only on "update" they are loaded to the "real" . But OC enable or disable should work always.))

Which chip we talking about here ? F405 , i see.

Try call "generate update event" (dont know how its name exactly) after your enable ,

or

just write to dis-/enable the matching value to CC register, "0" to disable and "your value" to enable pulse.

(I would do it this way , always.)

[waclawek.jan]

> (You writing values to the shadow registers, only on "update" they are loaded to the "real" . But OC enable or disable should work always.))

TIMx_CCER.CCxE bits *can* be preloaded, see TIMx_CCMR.CCPC (and .CCUS). However, this preload does not work through Update, but through the rather obscure Commutation event.

If this is the case, the Commutation event should be forced by setting TIMx_EGR.COMG, for the TIMx_CCER.CCxE bits to get active immediately. 

Observing TIMx_CR2 content would reveal the truth. However, the question then also is, why is there the preload set at the first place, and then if such forced Commutation would not spoil some grand scheme.

JW

[pf26]

Hello, thks a lot for your fast answers !

Unfortunately, still no luck, the system always wants some time before re-enabling the outputs - I just noticed that this time gets shorter when PWM frequency increases (approx 10ms at 40kHz, but 13ms at 30).

Rising TIMx_EGR.COMG or playing on other bits here and there according to yours hints did not change much the scene. I am not familiar with STM32 timers, I reuse a large code (from VESC motor controller), so it is very likely that I missed something - but where ?

[waclawek.jan]

Read out and check/post the timer registers' content.

JW

[AScha.3]

So

just write to dis-/enable the matching value to CC register, "0" to disable and "your value" to enable pulse.

[pf26 · Accepted solution]

Oups ! Sorry, My mistake. I was looking for something complicated when the answer was so simple: I had 3 flags to remember which output phase was already off, and because of copy/paste error and all of this was hard to read in macro format to inline it upon different places, I mixed up some flags. Sorry for bothering.

[waclawek.jan]

OK so problem solved?

If yes, please click on "Accept as solution" in your post so that the thread is marked as solved.

JW