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SiC inverter design - high switching frequency

Kiron Sen
Associate

I am designing a SiC inverter for a Formula SAE student team, using a 72MHz STM32F302CC with the motor control library. The desired switching frequency is 50-100kHz, depending on the device we select.

Reading the motor control manual, I discovered that "the FOC loop is... executed at the PWM frequency rate (That is: once every PWM Period)." Will I encounter any issues with the complex FOC loop executing so quickly on a 72MHz processor? The only extra processing I plan on doing is some simple state machine logic, receiving torque command CAN messages and sending status CAN messages.

I'm looking into using the STGAP1AS gate driver. Is 100kHz PWM output feasible considering reasonable parasitics? I understand that the typical MCU I/O pin capacitance is 5pF, the gate driver's input should be high impedance (but I can't figure that out from the datasheet), and the MCU and gate driver will reside relatively close on the same PCB.

I am using an F302 because all my other sub-systems use it, but am not opposed to upgrading if necessary to meet the 50-100kHz switching frequency requirement. Thanks!

1 ACCEPTED SOLUTION

Accepted Solutions
lauria.michele
Associate II

​Hi Kiron,

STGAP1AS has a maximum operating frequency of 150 kHz. The actual switching speed might be further limited by the gate driver power dissipation, which depends on the inverter stage characteristics (Qg of the power Switch, supply rails, gate resistors and so on).

The logic inputs of the device have internal pull-down resistors whose value is specified in the datasheet (Rin_pd parameter). If the MCU and gate drivers are on the same PCB there should be no issue in switching at 100 kHz. Please consider that a proper layout of the gate loop is very important as well.

regards

Michele Lauria

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1 REPLY 1
lauria.michele
Associate II

​Hi Kiron,

STGAP1AS has a maximum operating frequency of 150 kHz. The actual switching speed might be further limited by the gate driver power dissipation, which depends on the inverter stage characteristics (Qg of the power Switch, supply rails, gate resistors and so on).

The logic inputs of the device have internal pull-down resistors whose value is specified in the datasheet (Rin_pd parameter). If the MCU and gate drivers are on the same PCB there should be no issue in switching at 100 kHz. Please consider that a proper layout of the gate loop is very important as well.

regards

Michele Lauria