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Watchdog reset the CPU when CPU is halted.

RahulPatil_123
Associate

On nucleo_u575zi_q below observations has been captured.

Issue: - when IWDGRSTF flag is cleared by writing to the RMVF bit still watchdog reset occurred.
Expected Behavior: - When the IWDGRSTF flag is cleared by writing to the RMVF bit, the watchdog reset should not occur.

Please find the below snippet of sample code of STM32cubeIDE.

RahulPatil_123_0-1748583844403.png

Also find the reference of user Manul and data sheet of nucleo_u575zi_q board.

RahulPatil_123_1-1748583971134.pngRahulPatil_123_2-1748584003780.png

Please provide appropriate solution for the above issue.

3 REPLIES 3
Ozone
Principal

> Expected Behavior: - When the IWDGRSTF flag is cleared by writing to the RMVF bit, the watchdog reset should not occur.

Why do you expect such a behavior ?
Nowhere is stated that any access to said flag will stop the IWDG.

RahulPatil_123
Associate

RahulPatil_123_0-1748601457105.png

 
LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP);
what is meaning of above snippet code and above function can you please explain?
 
what does the below micro
 DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos
TDK
Super User

To halt IWDG during debug, set DBG_IWDG_STOP in DBGMCU_APB1LFZR.

TDK_0-1748610820195.png

 

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