2022-10-17 06:14 AM
Hello,
I am programming a USB device from scratch (for learning purposes) on a STM32F7 board.
It is a simple HID mouse.
Everything works great in the enumeration, my device is correctly recognized by the host (Windows PC) as a mouse. I've chose to use an IN endpoint in interrupt mode to send the report to the host.
When the enumeration is finished, the host starts sending IN token to the device, and asks for the report. However, the device seems to not receive any of these tokens, and so the device does not send any report but only 0-data-length packets.
I've checked the DAINT register, but the third bit (I use IN endpoint 3) never gets set.
I supposed it comes from the initialization of this endpoint, but I don't see what"s wrong. Here's my code:
// Unmasks all interrupts of the targeted IN endpoint 3.
USB_OTG_FS_DEVICE->DAINTMSK |= ( 1 << 3);
// Activates the endpoint, sets endpoint handshake to NAK (not ready to send data), sets DATA0 packet identifier
IN_ENDPOINT(3)->DIEPCTL &= ~(USB_OTG_DIEPCTL_MPSIZ | USB_OTG_DIEPCTL_EPTYP | USB_OTG_DIEPCTL_TXFNUM);
IN_ENDPOINT(3)->DIEPCTL |= (USB_OTG_DIEPCTL_USBAEP | USB_OTG_DIEPCTL_SNAK | USB_OTG_DIEPCTL_SD0PID_SEVNFRM);
IN_ENDPOINT(3)->DIEPCTL |= (ENDPOINT_64_SIZE << USB_OTG_DIEPCTL_MPSIZ_Pos); // max packet size = 64 bytes
IN_ENDPOINT(3)->DIEPCTL |= (ENDPOINT_INTERRUPT_TYPE << USB_OTG_DIEPCTL_EPTYP_Pos); // interrupt endpoint
IN_ENDPOINT(3)->DIEPCTL |= (3 << USB_OTG_DIEPCTL_TXFNUM_Pos); // assign TxFIFO_3 to the endpoint
I've also noticed in the debugger that the firmware cannot set the USB_OTG_DIEPCTL_SD0PID_SEVNFRM bit of the DIEPCTL_3 register, although it is written in the datasheet to be a R/W bit. But I don't think it can be the cause of this problem, as the feature of this bit is supposed to affect only the transmission and not the reception on the endpoint.
Thank you for any help.
Solved! Go to Solution.
2022-10-19 10:39 AM
Resolved, I had a typo somewhere else, the endpoint was stalled:
I've wrote REG &= STALL instead of REG &= ~STALL to clear the stall bit.
2022-10-19 10:39 AM
Resolved, I had a typo somewhere else, the endpoint was stalled:
I've wrote REG &= STALL instead of REG &= ~STALL to clear the stall bit.