Unstable SPI Slave

[Nikolaj_TL]

I have a custom board with a STMWB55 (master) and a STM32F031 (slave). They communicate over SPI using DMA. Unforturenately there are communication problems.

In order to identify the problem I have simplified the setup. I have used a ST NUCLEO-F031K6 and a ST NUCLEO-WB55 board to test the communication (SCLK, MISO & MOSI are used, 250kHz clk freq). Both use SPI example provided from ST (from STM32Cube_FW_F0_V1.11.5 and STM32Cube_FW_WB_V1.19.0). 
The slave is setup to use interrupt instead of DMA to get the simplest setup. The only modification made from the original example is that the Master sends 8x bytes messages and the slave echoes what it receives - in order to test the slave device. Approximately 200 bits out of 10kB from the slave are errorprone. The communication is monitored using a logic analyser and the data is analysed with python.

Is this success/failure rate expected? Is this something that you have come across before? Do you have suggestions for solutions?

Here is an example of an error from the test:

(the slave actually echoes the message received +1, in order to easily compare the messages)

[TDK]

> Is this success/failure rate expected? Is this something that you have come across before? Do you have suggestions for solutions?

You shouldn't be having random bits be incorrect. Noise can be a problem with long lead lines, if your clock rate is high. Using a CS pin is typically preferred, as it can allow for re-synchronization between master/slave.

> (the slave actually echoes the message received +1, in order to easily compare the messages)

But your output typically shows the same values (e.g.0x01/0x01), not X/X+1 (0x01/0x02)?

Perhaps zoom in on a transaction that failed within the logic analyzer to see and show more of what's going on.