2023-09-06 12:57 PM
Hello,
I have a Nucleo-U5A5ZJQ dev board and am attempting to get a minimum USB HS example working using the PCD HAL library. When `MX_USB_OTG_HS_PCD_Init()` is called, a HAL_TIMEOUT occurs when attempting a CoreReset using the `USB_OTG_GRSTCTL_CSRST`, specifically this line in stm32u5xx_ll_usb.c
/* Core Soft Reset */
count = 0U;
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
do
{
count++;
if (count > 200000U)
{
return HAL_TIMEOUT; <---- THIS LINE
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
return HAL_OK;
I have checked and confirmed that the USBPHYCEN and OTGEN bits are set in the AHB2ENR1 register before this function call. I have also confirmed that OTGHSPHYCR is enabled and set to 16Mhz (the USB PHY clock speed).
I'm currently out of ideas on what would be causing the USB peripheral to fail on initialization. My intuition is saying that it's clock related, but as far as I can tell, I have setup the clocks correctly according to the datasheet.
I've attached my project below. Any thoughts would be very much appreciated!
2024-01-25 06:10 AM
I'm quite puzzled how the CDC_ACM demo code dated 2021, working fine (no issue with USB corereset) that gets away without this statement, __HAL_RCC_SYSCFG_CLK_ENABLE();
I have looked into both 2021 (demo) and 2024 (V141) and still could not find something that activates the syscfg clock to work.
Do I need to disable SYSCFG_CLK after that is done? What is the best place to do this?