STM32N6 Example to initialize all available RAM using HAL or similar

[TheImmortal]

Hello there,

I cant find full working example about ram initializations and relevant RISAF settings,

I need to get at least 2.5MB region for camera data capture, I found clk and power enable functions, but it does not working, when I increase memory size in .ld file the code does not run...

I guess I use correct clk and power registers:

__HAL_RCC_AXISRAMx_MEM_CLK_ENABLE();

RAMCFG_SRAMx_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;

I use FSBL and my code will fit there not reaching 512KB limit.

CubeMX do not have a lot of settings there, RISAF do not have default values or some help hints which there can help, and there is no memory map window like let say for H7 and other mcu's...

How to correctly initialize and use all the RAM ?

Thanks.

[Saket_Om]

Hello @TheImmortal 

Could share your code please, then we can assist you more effectively. 

[TheImmortal]

There in code is initialized and used a lot of resources, most of them is working, for other I need to adjust/write functions and code, now I just need to increase buffer for DCMI DMA, to increase I need to enable RAM power and set access, I know how to deal with MPU and DMA because I have used for other peripherals and its working, and  I have full working prototype with 1.2mp DCMI camera DMA to external SDRAM on H7 mcu, there on N6 I need help to set up RAM for DCMI buffer, I increased RAM size in .ld file, build analyzer shows my new amount and compiler do not throw overflow RAM region error, I enabled power and clk for RAM but I am not sure if I did it correctly, below is part of code where I enabled CLK and power:

__HAL_RCC_AXISRAM3_MEM_CLK_ENABLE();
__HAL_RCC_AXISRAM4_MEM_CLK_ENABLE();
__HAL_RCC_AXISRAM5_MEM_CLK_ENABLE();
__HAL_RCC_AXISRAM6_MEM_CLK_ENABLE();

RAMCFG_SRAM3_AXI_NS->ERKEYR = 0xCA;
RAMCFG_SRAM3_AXI_NS->ERKEYR = 0x53;
__DSB();
__ISB();
// Power the RAM
RAMCFG_SRAM3_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;
RAMCFG_SRAM4_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;
RAMCFG_SRAM5_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;
RAMCFG_SRAM6_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;

I placed in /* USER CODE BEGIN SysInit */, there is correct place ?

Maybe there I need to set new ram region in .ld for DCMI buffer and don't touch current setup where is by default RAM set at 0x341C0000 with length 256K ?

If there is required to set RIFFS then provide some hints or example.

Oh yes, I forgot one moment while playing with RAM and buffer size, how to set DMA for DCMI if there is no active DMA handle's ? All is inactive in list. 

Thanks

---

Edited to apply source code formatting - please see How to insert source code for future reference.

[Saket_Om]

Hello @TheImmortal 

If the AXISRAMs are shutdown, since you are trying to clear the shutdown bits, I suppose the AXISRAMs are shutdown. In this case You must first exit shutdown. It is the sequence described in the RM (section 10.4).

[TheImmortal · Accepted solution]

I have enabled all the ram in FSBL, found some info in google and Saket_Om pointed to read manual again, I am not sure if everything is correct there, but there is working example (You need to adjust regions, because it depend on you setup and there is not everything is correct):

// settings in .ld file, you can change by you requirements:
/* Memories definition */
MEMORY
{
  ROM    (xrw)    : ORIGIN = 0x34180400,   LENGTH = 255K
  RAM    (xrw)    : ORIGIN = 0x341C0000,   LENGTH = 256K
  
  /* my tests*/
  RAMITCM (rwx)   : ORIGIN = 0x00000000, LENGTH = 64K
  RAMDTCM (rwx)   : ORIGIN = 0x20000000, LENGTH = 128K
  RAMRET  (rwx)   : ORIGIN = 0x24000000, LENGTH = 80K
  
  RAMFLEX (rwx)   : ORIGIN = 0x24014000, LENGTH = 320K
  RAMAXI1 (rwx)   : ORIGIN = 0x34064000, LENGTH = 624K  
  
  RAMCAM  (rwx)   : ORIGIN = 0x34200000, LENGTH = 2457600
  SDRAM	  (rwx)   : ORIGIN = 0xC0000000, LENGTH = 32M
  /* RTCRAM	(rwx)   : ORIGIN = 0x38800000, LENGTH = 4K */
}
  /* Used by the startup to initialize data */
  _sidata = LOADADDR(.data); /* add ram naming and setup after this line */

  .RAM_ITCM (NOLOAD):
  {
    . = ALIGN(4);
    KEEP(*(.RAM_ITCM))
  } >RAMITCM
  
    .RAM_DTCM (NOLOAD):
  {
    . = ALIGN(4);
    KEEP(*(.RAM_DTCM))
  } >RAMDTCM
  
    .RAM_RET (NOLOAD):
  {
    . = ALIGN(4);
    KEEP(*(.RAM_RET))
  } >RAMRET
    
  .RAM_CAM (NOLOAD):
  {
    . = ALIGN(4);
    KEEP(*(.RAM_CAM))
  } >RAMCAM

  .EX_SDRAM (NOLOAD) :
  {
    . = ALIGN(4);
    *(.sdram .sdram.*)
  } >SDRAM
  /* <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< */

// this setup is included in code
void nsDelay(uint32_t ns) {
    volatile uint32_t count = ns / 1.25; // 1.25 for 800mhz MCU clock
    while (count--) {
        __NOP();  // 1 cycle (~1ns on 100MHz+ CPU)
    }
}
/* USER CODE BEGIN SysInit */
  uint32 tstr;
    RAMCFG_SRAM3_AXI_NS->ERKEYR = 0xCA;
    RAMCFG_SRAM3_AXI_NS->ERKEYR = 0x53;
    __DSB();
    __ISB();
    __HAL_RCC_RAMCFG_CLK_ENABLE();
    // Power the RAM up by writing 0 to SRAMSD in RAMCFG_AXISRAMxCR
    RAMCFG_SRAM3_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD; // ~(RAMCFG_CR_SRAMSD | RAMCFG_CR_SRAMSLEEP);
    nsDelay(50);
    tstr = RAMCFG_SRAM3_AXI_NS->CR;
    __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE();

    RAMCFG_SRAM4_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;
    nsDelay(50);
    tstr = RAMCFG_SRAM4_AXI_NS->CR;
    __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE();

    RAMCFG_SRAM5_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;
    nsDelay(50);
    tstr = RAMCFG_SRAM5_AXI_NS->CR;
    __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE();

    RAMCFG_SRAM6_AXI_NS->CR &= ~RAMCFG_CR_SRAMSD;
    nsDelay(50);
    tstr = RAMCFG_SRAM6_AXI_NS->CR;
    __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE();


    RAMCFG_VENC_RAM_NS->CR &= ~RAMCFG_CR_SRAMSD;
    nsDelay(50);
    __HAL_RCC_VENCRAM_MEM_CLK_ENABLE();

    RAMCFG_BKPSRAM_NS->CR &= ~RAMCFG_CR_SRAMSD;
    nsDelay(50);
    __HAL_RCC_BKPSRAM_MEM_CLK_ENABLE();
  /* USER CODE END SysInit */
// and buffer initialization example, alignment is required for DMA use:
__attribute__ ((section(".RAM_CAM"))) uint16_t frame_buff_DCMI[frame_buff_DCMI_sz] __attribute__((aligned(4)));

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