STM32H7 MIPI DSI maximum clock speed?

[bchia]

There is inconsistency in the reference manual and the STM32CubeMX clock configuration tool as to what the maximum clock for the PLL DSI. Reference manual suggests it is 1000 MHz however, when set to that in STM32CubeMX, an error is generated at the PHY DSI lane byte frequency with a maximum of 62MHz instead of an expected 125MHz

[ofer-bahar]

this is how it looks on the STM32 Cube 1.17.0 MX clock settings

you can see clearly that 62.5Mhz is not allowed in the MX clock configurator !!!

what should a programmer do in that case ??