STM32H7 MIPI DSI maximum clock speed?

[bchia]

There is inconsistency in the reference manual and the STM32CubeMX clock configuration tool as to what the maximum clock for the PLL DSI. Reference manual suggests it is 1000 MHz however, when set to that in STM32CubeMX, an error is generated at the PHY DSI lane byte frequency with a maximum of 62MHz instead of an expected 125MHz

[Tesla DeLorean]

Not 1 GHz, but 1 Gbps via both edges on both lanes​

[Tesla DeLorean]

62 MHz is more of the word delivery clock​

62.5 MHz 32-bpp

83.3 MHz 24-bpp

DSI HOST, 500 MHz clock, signal on both edges, 1x lane 1 Gbps, 2x lane 2 Gbps

2000/24 -> 83.333

[bchia]

Yes its DDR on the output clock at but according to the RM the PLL puts out 1GHz. When using those setting CubeMX gives an error so I'm not sure if there is a hardware limitation or just software bug in CubeMX. Don't have hardware yet so can't test at the moment.

[peterdonchev]

For STM32H7 it is 1Gbps per lane - 2Gbps total.

[MM..1]

Is STM32U599 speed same ? and i mean you miss H7

STM32H7-Peripheral-DSI HOST interface (DSIHOST)

[peterdonchev]

Ahh, yeah, I mean dual core STM32H7 MCUs:
From STM32H747 datasheet:

From AN4860:

[Tesla DeLorean]

Because it's not funnelling BITS into the pipe it's either 16 or 24-bit words for the PIXEL. The 62.5 MHz is the PIXEL clock, the LTDC spits out the data as it paints the rasters, and the DSI needs to move it out at least that quickly.

The DSI PHY clocks at the high rate to push BITS out the LANES, 1 GHz in there is basically 500 MHz on the DSI bus itself.

62.5 MHz / 50 Hz refresh = 1.25 Mpixel

[peterdonchev]

Four years on and the confusion is still here. It's unclear whether this is a bug in CubeMX or a hardware limitation.