stm32h7 LTDC controller CLUTWR register config

[wangx]

hello, 

When configuring the STM2H7 LTDC display controller in CLUT mode, the CLUTWR register needs to be write. In the official example provided by STM32, the register is cycled 256 times to configure the CLUT table. This method of writing 256 times to a register in a loop is different from common sense. How should we understand this configuration method? or who can give me some other example as this config method, thanks!

for (counter = 0U; (counter < CLUTSize); counter++)
  {
		if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
    {
      tmp  = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
     }
    else
    {
      tmp  = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
    }

    pcolorlut++;

    /* Specifies the C-LUT address and RGB value */
    LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
  }

[ZKr]

Hello Wangx,

CLUT (Color Look-Up Table) mode is an efficient technique to minimize memory usage in displays for graphics with limited color depth. Instead of storing full RGB values for each pixel, the pixel data contains an 8-bit index referencing a palette of colors stored in the CLUT. This palette comprises 256 entries, each typically representing a 24-bit RGB color.

To program the CLUT, software sequentially writes each color entry to the write-only CLUT write register (LTDC_LxCLUTWR). Each 32-bit write encodes both the palette index (CLUT address) in bits 31:24 and the corresponding RGB color value in bits 23:0.

Since each write updates a single palette entry, a total ofCLUTSizewrites are required to fully configure the CLUT.

Best regards,
Zied

[waclawek.jan]

The Color LookUp Table (CLUT, sometimes called Palette) is a 256xRGB888 memory (i.e. 256 x (8+8+8)bits = 256 x 24 bits). As this memory is in the pixel-clock-domain rather than the APB clock domain (pclk), there is a synchronizer between these domains. This synchronizer would get a bit more complicated if it would need to transfer 256 memory words = registers (plus the remaining dozen-or-so other registers which are in the pixel-clock-domain, too); so as a simplification, the hardware designers added the 8-bit address (to address one of the 256 CLUT words) to be transferred together with the 24-bit data in a single write to LTDC_LxCLUTWR:

JW