STM32H523VE - High cycle flash pure read configuration

[Mks1]

Hi All,

I do struggle with high-cycle flash read.

By using the example:
https://github.com/STMicroelectronics/STM32CubeH5/tree/main/Projects/NUCLEO-H563ZI/Examples/FLASH/FLASH_EDATA_EraseProgram
It is doable to erase/write sector or halfword but reading from address (with simple memcpy) without writing/erasing it just before causes NMI_Handler().

How to init/configure the EFLASH to simply retrieve data after startup?


Write function: 
HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD_EDATA, address, (uint32_t)&halfword)

Read 'function':
uint16_t halfword = *(uint16_t*) address;

Regards,
Mat

[Saket_Om]

Hello @Mks1 

The NMI fault can be due to an ECC error detection. Could you check this point please?

[Mks1]

Thanks for the speedy reply and the hint!

By running:

uint16_t example_data = 0;

example_data = *(uint16_t*)(0x09000000U) ; //ECCCORR reg getting filled and the variable is 0xaa80

example_data = *(uint16_t*)(0x09000002U) ; //No change

example_data = *(uint16_t*)(0x09000004U) ; //After execution NMI Handler is called, ECCDETR reg getting filled

The memory content is:

And correction registers content:
FLASH->ECCCORR = 0100 0000 0010 0000 0011 0000 0000 0000
FLASH->ECCDETR =  1000 0000 0010 0000 0011 0000 0000 0001

Both registers points EDATA_ECC bit, what is:
EDATA_ECC: ECC fail for corrected ECC error in flash high-cycle data area
It indicates if flash high-cycle data area is concerned by ECC error.

What corresponds to the device behaviour. I have doubts about ECC error address:
Register description: The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area).

The address pointer is 0x3000 and 0x3001 what correspond to user flash (7.9.10)

Next step: I've tried to brute force these errors with:

example_data = *(uint16_t*)(0x09000000U) ; //ECCCORR reg getting filled

FLASH->ECCCORR |= 0x40000000; //clear status by writing 1 to correction flag field

FLASH->ECCDETR |= 0x40000000;

example_data = *(uint16_t*)(0x09000002U) ;//ECCCORR reg getting filled

FLASH->ECCCORR |= 0x40000000;

FLASH->ECCDETR |= 0x40000000;

example_data = *(uint16_t*)(0x09000004U) ;// Both ECCCORR and ECCDETR reg getting filled, NMI handler occurs


I've tried logic, coffee, and willpower — maybe you’ve got a smarter next step?

[Saket_Om]

Hello @Mks1 

The errors you are experiencing may be due to accessing the high-cycle data area of flash memory (0x0900_0000 - 0x0901_7FFF) before it has been properly enabled and configured. Please ensure that the EDATA enable and start configuration bits are correctly set prior to accessing this region, as per the reference manual.

[Mks1]

FLASH_EDATA1R_CUR just before and after is 1000 0000 0000 0111, what means that flash high-cycle data is enabled and the last eight sectors of Bank 1 are reserved for eeprom emulation:

In that case I ought to be able to read any data between 0x0900 0000 and 0x0900 BFFF. Correct me if I am wrong.

Reading from regular Flash memory (for instance 0x0800 0000) does not cause any trouble.

EDATA2 is zeroed.

Any ideas how to proceed with debugging?

[aa3]

我也想知道该如何解决，谢谢