STM32H5 and memory barriers usage in ICACHE/DCACHE APIs

magnus · ‎2025-04-11

Hello.

STM32H5
I'm used to cache operations using memory barriers (ISB/DSB), but looking at a function like HAL_ICACHE_Invalidate() or HAL_DCACHE_Invalidate() I can't find any. Are memory barriers not needed with STM32 ICACHE/DCACHE?

Saket_Om · ‎2025-04-14

Hello @magnus

Thank you for bringing this issue to our attention.

I reported this internally.

Internal ticket number: 207571 (This is an internal tracking number and is not accessible or usable by customers).

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Saket_Om