2025-04-11 2:14 AM - last edited on 2025-04-11 2:20 AM by mƎALLEm
Hello.
STM32H5
I'm used to cache operations using memory barriers (ISB/DSB), but looking at a function like HAL_ICACHE_Invalidate() or HAL_DCACHE_Invalidate() I can't find any. Are memory barriers not needed with STM32 ICACHE/DCACHE?
2025-04-14 6:01 AM
Hello @magnus
Thank you for bringing this issue to our attention.
I reported this internally.
Internal ticket number: 207571 (This is an internal tracking number and is not accessible or usable by customers).