STM32CubeIDE: HSI → PLL /2 not honored (Nucleo-F303RE, expected 36 MHz but runs at 72 MHz)

[Bhavil]

Hi Team,

I’m prototyping on a Nucleo-F303RE using STM32CubeIDE. In the clock configuration, I set the system clock to 36 MHz from HSI (HSI → PLL with the /2 divider), as shown in the clock tree screenshot.

However, my firmware misbehaved. After debugging, I found that SystemClock_Config() function isn’t applying the HSI/2 divider when feeding the PLL. Instead of:

  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;

CubeIDE generates:

  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;

This effectively makes the system clock 72 MHz instead of the configured 36 MHz.

Did I misconfigure something in the clock setup, or is this a CubeIDE code-generation bug when using HSI with the PLL /2 divider?

[Souhaib MAZHOUD]

Hello @Bhavil 

What is the version of the firmware and STM32CubeIDE used?