Need help working around USB OTG Errata (STM32L4S5VI)

[smitty.werberjagermanjensen]

Rev 4 of "STM32L4Rxxx and STM32L4Sxxx device errata" states that

"Data FIFO gets corrupted if the write sequence to the transmit FIFO is interleaved with other OTGFS register access"

and to work around it,

"Ensure that the transmit FIFO write accesses cannot be interrupted by a procedure performing accesses to the USB cell registers."

I'm attempting to implement USB CDC on STM32L4S5VI and I'm having trouble identifying exactly which sequences to prevent from being interrupted. Could you point me towards which registers and/or events I should be focusing on?

[waclawek.jan]

Interesting; this is very similar to what I found out in the hard way. I wonder when will this propagate into other synopsys-OTG-IP-containing parts' errata.

If you stick to a strictly interrupt-based USB implementation (and AFAIK ST's implementation is such), then this is not a problem, as both FIFO writes and all USB register accesses happen in the same ISR.

JW

[smitty.werberjagermanjensen]

Thank you for this response. It turned out to be quite illuminating.

I've found (so far) that I need to stick to the ISR-only implementation as you mention, but also that I seem to need to 'manually' chunk my transmissions to 64 byte packets or less.

Some packet inspection has shown that when the ST driver code breaks a larger block into 64-byte packets, it occasionally sends a 68 byte packet which botches the bus. If I tell it to send packets no more than 60 bytes long, it still sometimes sends a 64-byte packet which gives a CRC error but also confirms to the protocol (for bulk transfers at least).

I'm still investigating the packet length issue but my USB no longer locks up.

Thanks again.

[waclawek.jan]

> Some packet inspection has shown that when the ST driver code breaks a larger block into 64-byte packets, it occasionally sends a 68 byte packet

Huh.

Any clue what may cause this?

Couldn't the code write to other than full words, to word-aligned address in the USB FIFO?

What is the version of the Synopsys ID, as read out from GSNPSID register (offset 0x40, not documented in ST documentation)?

JW

[smitty.werberjagermanjensen]

As yet, I'm no further ahead in answering the questions about packet length, and after looking at the ID's I'm more puzzled because two different MCUs with the same USB IDs are responding differently to the "same" code. (I still need to examine deeper for code differences).

I have these ID's for all three boards I'm working with:

USB_OTG_FS->GSNPSID:   0x4f54330a
USB_OTG_FS->GHWCFG1:   0
USB_OTG_FS->GHWCFG2:   0x229ed520
USB_OTG_FS->GHWCFG3:   0x0200d1e8