I have been using a stm32f051 as a slave on i2c1 without any problem. Then I started to use it as a master on i2c2 at the same time. This caused the communication on i2c1 to fail with varying frequency. I have been using the i2c drivers with interrupt from the HAL library. I connected a logic analyzer to the i2c lines and located where the error occurred. The first image shows how the part where the error occurs should look like, where the master wants to read from a specific address (0x10) from the slave (the stm32) using a repeated start.
The last two images shows the same part of the communication on i2c1, only here is also communication on i2c2 (stm32 as master).
For some reason the stm32 sends a NACK on i2c1. The error only occurs when the communication on i2c1 and i2c2 are aligned in a specific way, as can be seen in the above images, where there is a write on i2c1 at the same time as a read starts on i2c2.
I couldn't find anything regarding this limitation in the reference manual. So I'm wondering if there is a known error with the i2c hardware that prevents this, or if there is something in the HAL drivers, or if I'm missing something else. All answers are appreciated.
