Issue in passing QSPI loader test case for custom STM32H750 board

[Gunaw77]

Good day everyone!

We are working with a custom PCB based on the STM32H750 Discovery board. We are trying to replace the existing MT25QL512ABB8ESF dual-bank setup with a dual S25FL512S setup (both driven with the same chip select).

I've got a board with the replacement S25FL512S ICs soldered on and am following the ST MOOC on QSPI flash loaders, but I'm running into issues in passing the recommended testing script; it fails at the memcmp function. 

As per the ST course, I created an empty project, set up the ioc file, and copy-pasted the user code section to the appropriate commented regions in the generated qspi c and h files from the repo, and I used the provided code from stm32-external-loader/QSPI_Drivers/MT25QL512/quadspi.h at contrib · STMicroelectronics/stm32-external-loader · GitHub .

I've reduced the SECTORS_COUNT to 3 for quicker debugging, commented out the MPU_Config function for now, and am watching the contents of a smaller buffer after calling the CSP_QSPI_EnableMemoryMappedMode function, but I keep reading out the same value (hex 0x99) from the memory locations mapped to the external flash chip - changing the contents of the initial buffer that is being sent to the external flash also doesn't seem to affect this value.

There is a significant difference between the way the Micron flash IC and the new S25FL512S need to be configured to enable Quad I/O operation, and in the way the initial latency cycle count needs to be specified, so advice on how I can verify if it's configured correctly would be appreciated.

I would appreciate ideas on how I could debug this to see exactly where I'm making a mistake.

More info: the pin config in the ioc file has been setup as follows (existing code in the ioc file is setup as a single bank config, but both chips are soldered on and the CS is shared). The board also has a push button latching circuit, so that code is also included in the main.c file. The QSPI clock input frequency is 90 MHz and the prescaler is 1, so my understanding is that it's running at 45 MHz. I have not yet tried generating the stldr file; if my code fails this test I assume that it'd fail there as well, and I would like to understand exactly where I'm making a mistake for the sake of personal learning. The provided code also seemed to repeat the reset block three times; I' don't understand the reason for this, since the datasheet simply states that the requirement is to wait for a certain number of microseconds.

Thank you very much for reading, and I hope you have a great day.

[_EFrie]

Hopefully someone steps in here and knows exactly, but I think you need to do a combination of debugging.

1. go to the trouble and connect up your logic analyzer, and slow the clock enough so things work.

2. fill the device with some type of pattern so you know what every position should be.

3. figure out whether it’s your writes or reads.

You have to think through the results, typically once you see the real results the problem becomes clear. Memory mapping makes it more difficult but it still should be doable. The analyzer makes it so you close the loop and know what the mcu is actually doing.

[Gunaw77]

Good morning! Thank you for the reply - burnt my logic analyser trying to do it and will be getting a replacement by tomorrow hopefully. In the mean time, I'm going to go to board with the old Flash chips (Micron) and will be testing the ST-supplied library for that chip with the test code as a sanity check, and then compare the implementation.