IRQ setting/controlling via NVIC or HAL?

[Pavel A.]

If you already use the HAL library then use it for NVIC as well.

HAL_NVIC_SetPriority vs. NVIC_SetPriority (CMSIS API) conveniently accepts plain values for the priority and hides confusing bit shifting.

[TDK]

Duplicate:

https://community.st.com/s/question/0D53W00001UVszwSAD/external-irq-control-via-cortex-library-or-via-hal-library

[Piranha]

By default subpriorities are not used and are almost useless anyway. Therefore they are not recommended. And, when subpriorities are not used, NVIC_SetPriority() doesn't need any bit shifting. As often, in real life usage ST's code is practically almost useless.

[LVara.1]

Many thanks, I will read, today , in Italy, is a holiday ... However, I had other unclear news: while traveling the web I found an email from 2020 that where a possible error is reported in the HAL_EXTI_xxxx:

https://community.st.com/s/question/0D50X0000CErIa2SQF/stm32f7-halextisetconfigline-configures-exti-incorrectly?t=1650091177992

I rewrote the code for a STM32F4 and in fact a perennial interrupt is generated. The question is now more general: when to use and why the HAL_NVIC_***, and when to use the HAL_EXTI_***? I have been using the HAL_NVIC_*** for a couple of years and have had no problems. I wanted to try the generation of software interrupts and I wanted to try the HAL_EXTI_*** (there is a specific call), but they were born many issues: The documentation does not seem very accurate, for example in the document UM1725-2021 on page 346, point 25.1.2 is written: "The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of EXTI_GPIOSel " Does it mean that I can activate at some time, for example PA0 and at another time PB0? It is not clear to me ... I have to do other tests or look for clearer documents. LV

[Piranha]

You have to learn what the NVIC and what EXTI is. NVIC is a peripheral internal to the ARM Cortex-M CPU core and manages interrupts from all peripherals. EXTI is a ST specific peripheral external to the CPU connected down at the APB2 bus and manages GPIO pin interrupts plus interrupts from some specific differently connected peripherals.