I3C issues with DMA, no hdmacr handle

[DanLumi]

Dear ST Community,

I'm trying to integrate I3C with DMA capability in my project (NUCLEO-H563ZI). Currently, I can run SPI/UART with DMA enabled, but I3C does not want to join the club (it works with IT, though).

After I configure DMA for I3C in the STM32CubeMX interface (GPDMA1):

RX CH2:

TX CH3:

And replace data transfer line:

HAL_I3C_Ctrl_Transmit_IT

to

HAL_I3C_Ctrl_Transmit_DMA

I face issues with the later function. Particularly, it fails confirming the existence of the hdmacr handle:

/* Check on hdmatx and hdmacr handle */
    else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL))

But I'm not sure what that means. The DMA handle from the DMA configuration tab is the same for both SPI/I3C since they both are in the same GPDMA 1:

• CH0: SPI TX.
• CH1: SPI RX.
• CH2: I3C TX.
• CH3: I3C RX.

My first question would be, can SPI/I3C live with the same GPDMA resource?

My second question, can I assign a different handle to I3C as they share the same names as in the SPI's TX/RX?

• TX: hdmatx
• RX: hdmarx

Any other clue/tip is greatly appreciated.

Thanks!

[Dor_RH]

Hello @DanLumi,

Unlike SPI, which requires two DMA channels (one for TX and one for RX), the I3C controller in controller mode needs three DMA channels:

• TX DMA channel (for data transmission)
• RX DMA channel (for data reception)
• CR DMA channel (for control/status register handling)

This third DMA channel (CR) is mandatory for I3C DMA operation and is why your current setup fails when the HAL driver checks for the presence of the hdmacr handle.

I hope my answer has helped you. When your question is answered, please select this topic as the solution that answered you, as it will help others find that answer faster.

Thanks for your contribution.

Dor_RH

[DanLumi]

Thanks @Dor_RH for taking a look at this. I will check this 3rd DMA channel for I3C and come back here reporting results.