2022-07-15 09:02 PM
I am using STM32F103ZET6 to work with TI ADS8688 via SPI interface.
Based on the sample program in STM32F10x_StdPeriph_Lib_V3.5.0 library, currently the basic function is OK, with SCK @ 9M.
Here is my program screenshot about clock and SPI configurations, (external crystal
@8M)
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void RCC_Configuration(void)
{
/* PCLK2 = HCLK/2 */
RCC_PCLK2Config(RCC_HCLK_Div2);
/* Enable SPI Master peripheral clocks --------------------------------------------------*/
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_SPI1, ENABLE);
}
/* SPI_MASTER configuration ------------------------------------------------*/
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
SPI_Init(SPI1, &SPI_InitStructure);
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However, with different sample rate of ADS8688, I need to change the SCK to higher frequency, such as 16M. (Since the highest working frequency of ADS8688 is 17M).
Although I can change the SPI_BaudRatePrescaler to 2, so as to get 18M SCK. It will exceed the max working frequency of ADS8688).
So would you please help to point out, how I can set the clock, or SPI configurations, to obtain higher SCK, that will closer to 17M frequency.
Thanks in advance.
2022-07-15 09:33 PM
The dividers don't work in your favour.
Clock the part at 64 MHz, rather than 72 MHz. As the flash is rather slow, and uncached, it might not execute code materially slower.
2022-07-16 12:57 AM
Another option would be to generate the clocks (SCK, NSS as needed) using a timer, feeding them externally to both the ADS8688 and SPI set a slave. Probably not something you can simply click in CubeMX.
JW
2022-07-16 03:16 AM
Despite the name used by HAL and the CR1 register, the SPI does not have a baud rate generator, but a simple divisor of the system clock frequency (limited to power of 2!!!) .
So in general to get the required speed in SPI you have to degrade the general performance of the MCU by reducing its system clock.
In more advanced MCUs there are multiple PLLs, so the speed of some peripherals is relatively independent of the system clock.
2022-07-16 05:40 PM
Thanks for your great suggestions and ideas, which were reasonable to me. Advanced MCUs with multiple PLLs could be a good option in future. Next step, I am going to try to reduce system clock to 64MHz, and find the balance between them firstly.
I will update here, after further results were found.
2022-07-16 10:05 PM
Because SPI has a restrictive clock divider, its clock source is as well. Power of 2 being the restriction, usually on SYSCLK unless SPI has input clock source mux.
2022-07-17 09:04 PM
Sounds a good idea. I never used external clock source for SPI Master before. It increase my knowledge of that field. Thanks for sharing.