I'm programming one of the dual-core STM32s (the STM32H747IGT6) and running into a situation where the CM4 is much slower than I need it to be, and I'm trying to figure out why.
I'm using this short piece of code as my test bed:
__COMPILER_BARRIER();
start_timer = TIM5->CNT;
if ( (loopState == WaitingToStoreValues) && (i < last_i) )
{
num_data = 0;
loopState = StoringValues;
}
end_timer = TIM5->CNT;
__COMPILER_BARRIER();
start_timer, loopState, i, last_i, and num_data are all stack variables, and TIM5 is set to run at full speed (240 MHz) so it ticks once every 4.1666 nsec.
The conditions in the 'if' statement are rarely met, and when I run this code a gazillion times the delta is 56 ticks 99% of the time so I'm assuming that's the "condition not met" situation. The rest of the time the delta is anywhere from 18 to 84 ticks.
I tried bracketing with __disable_irq/__enable_irq and it made no difference, so it's not IRQs causing the slowdown.
Is what I'm seeing consistent with the instruction read-ahead feature of the CM4?
Is there any chance that there is resource contention with the CM7? The CM4 is using SRAM3 for its RAM and the CM7 isn't using SRAM3 at all, but I'm not sure if there's some kind of bus contention going on.
