I’m working with an STM32G0 running ThreadX (Azure RTOS).
The system UART is configured in circular DMA mode with an IDLE event interrupt for data reception.
Symptoms
Intermittently, after hundreds of successful receptions, the system enters HardFault_Handler.
The fault always occurs at the same point in the code (on a C division instruction, inside a function unrelated to DMA).
The register values at the HardFault are shown in Image 1.
When it runs without triggering a hard fault, the registers are:
xPSR = 0x01000000 and CONTROL = 2.
When the hard fault occurs, these registers are:
xPSR = 0x00000000 and CONTROL = 0.
The failure does not depend on the received data.
The thread stack (PSP) has sufficient space.
I believe the intermittent HardFault is not related to the operation itself:
If I modify the code—adding new instructions or removing code—sometimes it reproduces, and other times it still reproduces but in different parts of the code.
Question
What can I do to determine the root cause of this hard fault? I can’t figure out what the problem is.
